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Lab 5

Super incredible Caches and Main Memory

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Topic	Posts	Views	Last Post
Lab5 Checkedoff By Alan Tse on Tue Nov 04, 2003 01:31 AM	2	65	By Michael Chen on Tue Nov 04, 2003 03:11 AM
Status 3pm Sunday By Brandon Ooi on Sun Nov 02, 2003 10:55 PM	1	29	By Brandon Ooi on Sun Nov 02, 2003 10:55 PM
Sunday By Alan Tse on Sun Nov 02, 2003 10:23 PM	1	30	By Alan Tse on Sun Nov 02, 2003 10:23 PM
Status report By Alan Tse on Sun Nov 02, 2003 02:22 AM	1	30	By Alan Tse on Sun Nov 02, 2003 02:22 AM
SRAM block By Michael Chen on Sun Nov 02, 2003 02:15 AM	1	65	By Michael Chen on Sun Nov 02, 2003 02:15 AM
USE CVS By Alan Tse on Sun Nov 02, 2003 12:26 AM	4	34	By Alan Tse on Sun Nov 02, 2003 02:14 AM
Plan of attack for this weekend By Michael Chen on Sat Nov 01, 2003 04:10 AM	3	34	By Michael Chen on Sat Nov 01, 2003 11:11 PM
Modelsim Crashing By Alan Tse on Sat Nov 01, 2003 10:58 PM	1	33	By Alan Tse on Sat Nov 01, 2003 10:58 PM
The buffer By Jason Murray on Thu Oct 30, 2003 07:40 AM	1	29	By Jason Murray on Thu Oct 30, 2003 07:40 AM
Status on Board Part II By Brandon Ooi on Thu Oct 30, 2003 07:06 AM	1	31	By Brandon Ooi on Thu Oct 30, 2003 07:06 AM
Status on Board By Alan Tse on Wed Oct 29, 2003 07:15 AM	1	32	By Alan Tse on Wed Oct 29, 2003 07:15 AM
Monday night into Tuesday By Brian Wolf on Wed Oct 29, 2003 04:41 AM	2	33	By Alan Tse on Wed Oct 29, 2003 07:12 AM
Processor now runs again. By Alan Tse on Wed Oct 29, 2003 12:03 AM	1	47	By Alan Tse on Wed Oct 29, 2003 12:03 AM
victim cache is ready By Michael Chen on Tue Oct 28, 2003 11:06 AM	2	32	By Alan Tse on Tue Oct 28, 2003 09:59 PM
Datapath Working in Simulation By Brandon Ooi on Tue Oct 28, 2003 10:45 AM	4	36	By Alan Tse on Tue Oct 28, 2003 09:57 PM
Synplify Warnings - Learn to code Biatches! By Alan Tse on Tue Oct 28, 2003 09:48 PM	1	137	By Alan Tse on Tue Oct 28, 2003 09:48 PM
Cache/board testing (brian) By Brandon Ooi on Tue Oct 28, 2003 10:47 AM	1	28	By Brandon Ooi on Tue Oct 28, 2003 10:47 AM
Monday By Alan Tse on Tue Oct 28, 2003 12:33 AM	2	31	By Michael Chen on Tue Oct 28, 2003 02:51 AM
Victim, cache and memController By Michael Chen on Mon Oct 27, 2003 08:24 PM	1	41	By Michael Chen on Mon Oct 27, 2003 08:24 PM
Status Report By Alan Tse on Mon Oct 27, 2003 10:33 AM	1	33	By Alan Tse on Mon Oct 27, 2003 10:33 AM
Sunday By Brian Wolf on Sun Oct 26, 2003 10:18 AM	3	33	By Michael Chen on Mon Oct 27, 2003 12:05 AM
Cause of errors, hazardDetect? By Alan Tse on Sat Oct 25, 2003 09:58 AM	2	26	By Michael Chen on Sun Oct 26, 2003 02:59 AM
memController error By Michael Chen on Fri Oct 24, 2003 03:28 AM	2	31	By Alan Tse on Sat Oct 25, 2003 09:48 AM
Modules specification By Alan Tse on Fri Oct 17, 2003 12:02 AM	9	51	By Alan Tse on Thu Oct 23, 2003 09:56 PM
writeBuffer.v bug report: By Alan Tse on Tue Oct 21, 2003 06:10 AM	1	28	By Alan Tse on Tue Oct 21, 2003 06:10 AM

1 2 > >> (Page 1 of 2)

enPath Discussion

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Lab 5

Lab5 Checkedoff

Status 3pm Sunday

Sunday

Status report

SRAM block

USE CVS

Plan of attack for this weekend

Modelsim Crashing

The buffer

Status on Board Part II

Status on Board

Monday night into Tuesday

Processor now runs again.

victim cache is ready

Datapath Working in Simulation

Synplify Warnings - Learn to code Biatches!

Cache/board testing (brian)

Monday

Victim, cache and memController

Status Report

Sunday

Cause of errors, hazardDetect?

memController error

Modules specification

writeBuffer.v bug report:

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Lab 5