Alan Tse - 2003-10-27

If you run the current incarnation, pay attention to PC at 300. We're losing the branch delay while the branch must stall for a load word.

Issue we needa consider. I'm expecting the address headed into the instMem, to stay the SAME when we first see the a stall signal, and to only change 1 cycle after the stall is low. Because when the instMem is stalled, it should only be worried about servicing the request DIRECTLY before the stall goes high, and not the request AS the stall goes high.

So there are two cases.
Normal stall, the address going in before the stall's value is VALID, therefore instMem should return the data at the address as soon as the miss goes low. The next cycle after it handles the next address which is saved.

InstMiss, the address going in before the stall must be LOOKEDUP, so whatever is returned right at the miss signal must be ignored. Again, the cycle after miss goes low, we should process the next address.

Right now we're having instMem correct for the poor behavior of its inputs, which is why instMem is so complicated. This also causes a whole slew of bugs I've been trying to kill for the whole weekend.