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Lab 4

Pipelined Processor Design

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Topic	Posts	Views	Last Post
Timing summary By Alan Tse on Wed Oct 15, 2003 04:44 AM	1	79	By Alan Tse on Wed Oct 15, 2003 04:44 AM
Lut Usage By Alan Tse on Wed Oct 15, 2003 03:26 AM	2	40	By Alan Tse on Wed Oct 15, 2003 04:41 AM
State of the Project: Screwed By Alan Tse on Mon Oct 13, 2003 11:52 AM	5	29	By Michael Chen on Tue Oct 14, 2003 07:56 AM
WE MAY HAVE LOST THE BATTLE... By Brandon Ooi on Tue Oct 14, 2003 05:26 AM	2	34	By Brandon Ooi on Tue Oct 14, 2003 05:53 AM
State of the Synthesis By Alan Tse on Sat Oct 11, 2003 12:16 AM	6	31	By Michael Chen on Mon Oct 13, 2003 06:29 PM
Mike's update By Michael Chen on Mon Oct 13, 2003 11:54 AM	2	36	By Michael Chen on Mon Oct 13, 2003 06:09 PM
Bug: 0 InstMem isn't being read. By Alan Tse on Mon Oct 13, 2003 09:09 AM	1	35	By Alan Tse on Mon Oct 13, 2003 09:09 AM
Multiply test By Brandon Ooi on Mon Oct 13, 2003 08:06 AM	1	28	By Brandon Ooi on Mon Oct 13, 2003 08:06 AM
monitor.v is modified By Michael Chen on Mon Oct 13, 2003 07:51 AM	1	33	By Michael Chen on Mon Oct 13, 2003 07:51 AM
Big - Multiply stall late [FIX0r3d] By Brandon Ooi on Mon Oct 13, 2003 07:22 AM	1	30	By Brandon Ooi on Mon Oct 13, 2003 07:22 AM
Bug - Stall signal becoming unknown [FIXED] By Brandon Ooi on Mon Oct 13, 2003 01:56 AM	1	31	By Brandon Ooi on Mon Oct 13, 2003 01:56 AM
Bug Lw when Addr changes - Datamem By Brandon Ooi on Mon Oct 13, 2003 01:09 AM	1	31	By Brandon Ooi on Mon Oct 13, 2003 01:09 AM
Bug Lw follwing a Sw [SOLVED] By Brandon Ooi on Mon Oct 13, 2003 01:07 AM	1	31	By Brandon Ooi on Mon Oct 13, 2003 01:07 AM
WE ARE BEING EXTERMINATED BY A BUG BUT ARE FI By Brandon Ooi on Sun Oct 12, 2003 09:52 AM	3	30	By Michael Chen on Sun Oct 12, 2003 08:45 PM
WE HAVE LOCATED AND EXTERMINATED THE FOLLOWIN By Brandon Ooi on Sun Oct 12, 2003 05:44 AM	1	33	By Brandon Ooi on Sun Oct 12, 2003 05:44 AM
Status of Proc. w/ forwarding and hazard By Brandon Ooi on Sun Oct 12, 2003 12:34 AM	1	37	By Brandon Ooi on Sun Oct 12, 2003 12:34 AM
Brandon taking over schematic By Brandon Ooi on Sat Oct 11, 2003 04:47 AM	2	43	By Brandon Ooi on Sat Oct 11, 2003 11:24 PM
dataHazard only looks at id if? By Brandon Ooi on Wed Oct 01, 2003 07:17 PM	6	32	By Michael Chen on Sat Oct 11, 2003 07:15 AM
module with clk needs RESET also By Michael Chen on Sat Oct 11, 2003 07:12 AM	1	30	By Michael Chen on Sat Oct 11, 2003 07:12 AM
Specifications: Due Tuesday Sept 30 By Alan Tse on Tue Sep 30, 2003 11:55 PM	27	74	By Alan Tse on Sat Oct 11, 2003 04:47 AM
CPU w/o Forwarding and HazardDetect WORKING By Brandon Ooi on Sat Oct 11, 2003 02:33 AM	1	32	By Brandon Ooi on Sat Oct 11, 2003 02:33 AM
Monitor bugs Part II [FIXED] By Brandon Ooi on Sat Oct 11, 2003 12:00 AM	1	36	By Brandon Ooi on Sat Oct 11, 2003 12:00 AM
Synplify Warnings By Alan Tse on Fri Oct 10, 2003 11:40 PM	1	45	By Alan Tse on Fri Oct 10, 2003 11:40 PM
My weekend status By Brian Wolf on Fri Oct 10, 2003 10:00 AM	1	36	By Brian Wolf on Fri Oct 10, 2003 10:00 AM
Schematic diagram available? By Brandon Ooi on Tue Oct 07, 2003 04:58 AM	2	35	By Brian Wolf on Fri Oct 10, 2003 03:30 AM

1 2 3 > >> (Page 1 of 3)

enPath Discussion

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Lab 4

Timing summary

Lut Usage

State of the Project: Screwed

WE MAY HAVE LOST THE BATTLE...

State of the Synthesis

Mike's update

Bug: 0 InstMem isn't being read.

Multiply test

monitor.v is modified

Big - Multiply stall late [FIX0r3d]

Bug - Stall signal becoming unknown [FIXED]

Bug Lw when Addr changes - Datamem

Bug Lw follwing a Sw [SOLVED]

WE ARE BEING EXTERMINATED BY A BUG BUT ARE FI

WE HAVE LOCATED AND EXTERMINATED THE FOLLOWIN

Status of Proc. w/ forwarding and hazard

Brandon taking over schematic

dataHazard only looks at id if?

module with clk needs RESET also

Specifications: Due Tuesday Sept 30

CPU w/o Forwarding and HazardDetect WORKING

Monitor bugs Part II [FIXED]

Synplify Warnings

My weekend status

Schematic diagram available?

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Lab 4