Design Summary
--------------
Number of errors: 0
Number of warnings: 1
Logic Utilization:
Number of Slice Flip Flops: 1,724 out of 38,400 4%
Number of 4 input LUTs: 3,813 out of 38,400 9%
Logic Distribution:
Number of occupied Slices: 2,514 out of 19,200 13%
Number of Slices containing only related logic: 2,514 out of 2,514 100%
Number of Slices containing unrelated logic: 0 out of 2,514 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 3,831 out of 38,400 9%
Number used as logic: 3,813
Number used as a route-thru: 18
Number of bonded IOBs: 88 out of 512 17%
Number of Block RAMs: 32 out of 160 20%
Number of GCLKs: 3 out of 4 75%
Number of GCLKIOBs: 1 out of 4 25%
Number of DLLs: 1 out of 8 12%
Total equivalent gate count for design: 572,724
Additional JTAG gate count for IOBs: 4,272
Peak Memory Usage: 140 MB
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Design Summary
--------------
Number of errors: 0
Number of warnings: 1
Logic Utilization:
Number of Slice Flip Flops: 1,689 out of 38,400 4%
Number of 4 input LUTs: 3,730 out of 38,400 9%
Logic Distribution:
Number of occupied Slices: 2,474 out of 19,200 12%
Number of Slices containing only related logic: 2,474 out of 2,474 100%
Number of Slices containing unrelated logic: 0 out of 2,474 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 3,748 out of 38,400 9%
Number used as logic: 3,730
Number used as a route-thru: 18
Number of bonded IOBs: 89 out of 512 17%
Number of Block RAMs: 32 out of 160 20%
Number of GCLKs: 2 out of 4 50%
Number of GCLKIOBs: 1 out of 4 25%
Number of DLLs: 1 out of 8 12%
Total equivalent gate count for design: 571,784
Additional JTAG gate count for IOBs: 4,320
Peak Memory Usage: 140 MB
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Design Summary
--------------
Number of errors: 0
Number of warnings: 1
Logic Utilization:
Number of Slice Flip Flops: 1,724 out of 38,400 4%
Number of 4 input LUTs: 3,813 out of 38,400 9%
Logic Distribution:
Number of occupied Slices: 2,514 out of 19,200 13%
Number of Slices containing only related logic: 2,514 out of 2,514 100%
Number of Slices containing unrelated logic: 0 out of 2,514 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 3,831 out of 38,400 9%
Number used as logic: 3,813
Number used as a route-thru: 18
Number of bonded IOBs: 88 out of 512 17%
Number of Block RAMs: 32 out of 160 20%
Number of GCLKs: 3 out of 4 75%
Number of GCLKIOBs: 1 out of 4 25%
Number of DLLs: 1 out of 8 12%
Total equivalent gate count for design: 572,724
Additional JTAG gate count for IOBs: 4,272
Peak Memory Usage: 140 MB
Design Summary
--------------
Number of errors: 0
Number of warnings: 1
Logic Utilization:
Number of Slice Flip Flops: 1,689 out of 38,400 4%
Number of 4 input LUTs: 3,730 out of 38,400 9%
Logic Distribution:
Number of occupied Slices: 2,474 out of 19,200 12%
Number of Slices containing only related logic: 2,474 out of 2,474 100%
Number of Slices containing unrelated logic: 0 out of 2,474 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 3,748 out of 38,400 9%
Number used as logic: 3,730
Number used as a route-thru: 18
Number of bonded IOBs: 89 out of 512 17%
Number of Block RAMs: 32 out of 160 20%
Number of GCLKs: 2 out of 4 50%
Number of GCLKIOBs: 1 out of 4 25%
Number of DLLs: 1 out of 8 12%
Total equivalent gate count for design: 571,784
Additional JTAG gate count for IOBs: 4,320
Peak Memory Usage: 140 MB