Anything generated by topLevel, dataBoardRam, instBoardRam is ok.
Everything else is an error.
@W: databoardram.v(58): No assignment to memoryLines_0_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_1_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_2_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_3_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_4_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_5_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_6_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_7_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_8_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_9_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_10_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_11_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_12_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_13_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_14_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_15_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_16_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_17_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_18_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_19_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_20_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_21_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_22_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_23_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_24_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_25_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_26_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_27_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_28_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_29_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_30_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_31_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(60): No assignment to tempcount @W:"u:\lab4\databoardram.v":60:4:60:13
@W: hazarddetect.v(43): Input break is unused @W:"u:\lab4\hazarddetect.v":43:8:43:13
@W: instboardram.v(58): No assignment to memoryLines_0_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_1_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_2_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_3_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_4_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_5_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_6_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_7_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_8_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_9_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_10_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_11_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_12_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_13_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_14_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_15_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_16_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_17_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_18_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_19_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_20_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_21_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_22_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_23_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_24_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_25_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_26_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_27_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_28_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_29_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_30_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_31_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(60): No assignment to tempcount @W:"u:\lab4\instboardram.v":60:4:60:13
@W: instmem.v(16): Port width mismatch for port we. Formal has width 1, Actual 32 @W:"u:\lab4\instmem.v":16:52:16:57
@W: mux4.v(15): Incomplete sensitivity list - assuming completeness @W:"u:\lab4\mux4.v":15:13:15:37
@W: mux4.v(21): Referenced variable in3 is not in sensitivity list @W:"u:\lab4\mux4.v":21:13:21:16
@W: regfile.v(27): Register 'file_0_' is only assigned 0 or its old value; the register will be removed @W:"u:\lab4\regfile.v":27:0:27:6
@W: shifter.v(11): Input logical is unused @W:"u:\lab4\shifter.v":11:22:11:29
@W: monitor.v(96): Ignoring initial statement @W:"u:\lab4\monitor.v":96:3:96:10
@W: monitor.v(13): Input clk is unused @W:"u:\lab4\monitor.v":13:9:13:12
@W: monitor.v(14): Input address is unused @W:"u:\lab4\monitor.v":14:16:14:23
@W: monitor.v(15): Input instruction is unused @W:"u:\lab4\monitor.v":15:2:15:13
@W: monitor.v(16): Input memOutput is unused @W:"u:\lab4\monitor.v":16:2:16:11
@W: monitor.v(17): Input regOutA is unused @W:"u:\lab4\monitor.v":17:2:17:9
@W: monitor.v(18): Input regOutB is unused @W:"u:\lab4\monitor.v":18:2:18:9
@W: monitor.v(19): Input aluOut is unused @W:"u:\lab4\monitor.v":19:2:19:8
@W: monitor.v(20): Input nextPc is unused @W:"u:\lab4\monitor.v":20:9:20:15
@W: monitor.v(22): Input stall is unused @W:"u:\lab4\monitor.v":22:10:22:15
@W: cpu.v(225): Undriven input idBranch, tying to 0 @W:"u:\lab4\cpu.v":225:69:225:77
@W: cpu.v(225): Undriven input idPcSrc, tying to 0 @W:"u:\lab4\cpu.v":225:81:225:88
@W: cpu.v(226): Undriven input exJal, tying to 0 @W:"u:\lab4\cpu.v":226:4:226:9
@W: cpu.v(226): Undriven input exLui, tying to 0 @W:"u:\lab4\cpu.v":226:35:226:40
@W: cpu.v(227): Undriven input memMemToReg, tying to 0 @W:"u:\lab4\cpu.v":227:4:227:15
@W: cpu.v(227): Undriven input wbRw, tying to 0 @W:"u:\lab4\cpu.v":227:20:227:24
@W: cpu.v(227): Undriven input wbRegWr, tying to 0 @W:"u:\lab4\cpu.v":227:29:227:36
@W: cpu.v(253): Undriven input idAluSrc, tying to 0 @W:"u:\lab4\cpu.v":253:24:253:32
@W: cpu.v(253): Undriven input idMemWrEnb, tying to 0 @W:"u:\lab4\cpu.v":253:37:253:47
@W: cpu.v(253): Undriven input idBranch, tying to 0 @W:"u:\lab4\cpu.v":253:52:253:60
@W: cpu.v(253): Undriven input idBez, tying to 0 @W:"u:\lab4\cpu.v":253:65:253:70
@W: cpu.v(255): Undriven input idPcSrc, tying to 0 @W:"u:\lab4\cpu.v":255:7:255:14
@W: cpu.v(255): Undriven input exRegWrEnb, tying to 0 @W:"u:\lab4\cpu.v":255:19:255:29
@W: cpu.v(255): Undriven input exMemToReg, tying to 0 @W:"u:\lab4\cpu.v":255:34:255:44
@W: cpu.v(255): Undriven input exCoProc, tying to 0 @W:"u:\lab4\cpu.v":255:49:255:57
@W: cpu.v(255): Undriven input memMemToReg, tying to 0 @W:"u:\lab4\cpu.v":255:62:255:73
@W: cpu.v(257): Undriven input break, tying to 0 @W:"u:\lab4\cpu.v":257:41:257:46
@W: cpu.v(257): Undriven input idRs, tying to 0 @W:"u:\lab4\cpu.v":257:51:257:55
@W: cpu.v(257): Undriven input idRt, tying to 0 @W:"u:\lab4\cpu.v":257:60:257:64
@W: cpu.v(257): Undriven input exRw, tying to 0 @W:"u:\lab4\cpu.v":257:69:257:73
@W: cpu.v(259): Undriven input memRw, tying to 0 @W:"u:\lab4\cpu.v":259:7:259:12
@W: processor.v(21): Port width mismatch for port stat. Formal has width 7, Actual 8 @W:"u:\lab4\processor.v":21:66:21:70
@W: toplevel.v(143): *Output RJ45_TRC has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":143:18:143:26
@W: toplevel.v(144): *Output RJ45_BRC has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":144:18:144:26
@W: toplevel.v(145): *Output RJ45_TLC has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":145:18:145:26
@W: toplevel.v(146): *Output RJ45_BLC has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":146:18:146:26
@W: toplevel.v(152): *Output PHY_ADD_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":152:18:152:26
@W: toplevel.v(156): *Output PHY_MDC has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":156:13:156:20
@W: toplevel.v(157): *Output PHY_MDDIS has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":157:13:157:22
@W: toplevel.v(158): *Output PHY_PWRDN has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":158:13:158:22
@W: toplevel.v(159): *Output PHY_RESET has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":159:13:159:22
@W: toplevel.v(160): *Output PHY_FDE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":160:13:160:20
@W: toplevel.v(161): *Output PHY_AUTOENA has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":161:13:161:24
@W: toplevel.v(162): *Output PHY_BYPSCR has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":162:13:162:23
@W: toplevel.v(163): *Output PHY_CFG_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":163:18:163:26
@W: toplevel.v(175): *Output PHY_TX_ER_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":175:18:175:28
@W: toplevel.v(177): *Output PHY_TX_EN_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":177:18:177:28
@W: toplevel.v(178): *Output PHY_TXD0_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":178:18:178:27
@W: toplevel.v(179): *Output PHY_TXD1_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":179:18:179:27
@W: toplevel.v(180): *Output PHY_TXD2_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":180:18:180:27
@W: toplevel.v(181): *Output PHY_TXD3_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":181:18:181:27
@W: toplevel.v(184): *Output PHY_TRSTE_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":184:18:184:28
@W: toplevel.v(189): *Output AP_SDATA_IN has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":189:13:189:24
@W: toplevel.v(190): *Output AP_SYNC has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":190:13:190:20
@W: toplevel.v(191): *Output AP_RESET_B has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":191:13:191:23
@W: toplevel.v(192): *Output AP_PC_BEEP has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":192:13:192:23
@W: toplevel.v(194): *Output AA_MUTE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":194:13:194:20
@W: toplevel.v(198): *Output RAM_CLK has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":198:19:198:26
@W: toplevel.v(199): *Output RAM_CLKE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":199:19:199:27
@W: toplevel.v(200): *Output RAM_DQMH has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":200:19:200:27
@W: toplevel.v(201): *Output RAM_DQML has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":201:19:201:27
@W: toplevel.v(202): *Output RAM_CS has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":202:19:202:25
@W: toplevel.v(203): *Output RAM_RAS has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":203:19:203:26
@W: toplevel.v(204): *Output RAM_CAS has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":204:19:204:26
@W: toplevel.v(205): *Output RAM_WE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":205:19:205:25
@W: toplevel.v(206): *Output RAM_BA has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":206:24:206:30
@W: toplevel.v(207): *Output RAM_A has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(215): *Output ACE_MPIRQ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":215:13:215:22
@W: toplevel.v(216): *Output ACE_MPCE_B has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":216:13:216:23
@W: toplevel.v(217): *Output ACE_MPWE_B has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":217:13:217:23
@W: toplevel.v(218): *Output ACE_MPOE_B has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":218:13:218:23
@W: toplevel.v(219): *Output ACE_MPA has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(223): *Output VE_P has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(225): *Output VE_SDA has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":225:13:225:19
@W: toplevel.v(227): *Output VE_RESET_B has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":227:13:227:23
@W: toplevel.v(231): *Output VE_SCRESET has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":231:13:231:23
@W: toplevel.v(233): *Output VE_CLKIN_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":233:13:233:22
@W: toplevel.v(242): *Output VD_RESET_B has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":242:13:242:23
@W: toplevel.v(298): *Output SEG_PT_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(259): *Output PINOUT_TOP_CLOSE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(260): *Output PINOUT_TOP_FAR has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(261): *Output PINOUT_LEFT_CLOSE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(262): *Output PINOUT_LEFT_FAR has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(263): *Output PINOUT_BOTTOM_CLOSE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(264): *Output PINOUT_BOTTOM_FAR has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(265): *Output PINOUT_RIGHT_CLOSE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(266): *Output PINOUT_RIGHT_FAR has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(149): Input PHY_LEDCLK is unused @W:"u:\lab4\toplevel.v":149:11:149:21
@W: toplevel.v(150): Input PHY_LEDDAT is unused @W:"u:\lab4\toplevel.v":150:12:150:22
@W: toplevel.v(151): Input PHY_LEDENA is unused @W:"u:\lab4\toplevel.v":151:12:151:22
@W: toplevel.v(154): Input PHY_MDIO is unused @W:"u:\lab4\toplevel.v":154:12:154:20
@W: toplevel.v(155): Input PHY_MDINT is unused @W:"u:\lab4\toplevel.v":155:12:155:21
@W: toplevel.v(164): Input PHY_LED0_ is unused @W:"u:\lab4\toplevel.v":164:18:164:27
@W: toplevel.v(165): Input PHY_LED1_ is unused @W:"u:\lab4\toplevel.v":165:18:165:27
@W: toplevel.v(166): Input PHY_LED2_ is unused @W:"u:\lab4\toplevel.v":166:18:166:27
@W: toplevel.v(167): Input PHY_LED3_ is unused @W:"u:\lab4\toplevel.v":167:18:167:27
@W: toplevel.v(168): Input PHY_RXD0_ is unused @W:"u:\lab4\toplevel.v":168:18:168:27
@W: toplevel.v(169): Input PHY_RXD1_ is unused @W:"u:\lab4\toplevel.v":169:18:169:27
@W: toplevel.v(170): Input PHY_RXD2_ is unused @W:"u:\lab4\toplevel.v":170:18:170:27
@W: toplevel.v(171): Input PHY_RXD3_ is unused @W:"u:\lab4\toplevel.v":171:18:171:27
@W: toplevel.v(172): Input PHY_RX_DV_ is unused @W:"u:\lab4\toplevel.v":172:18:172:28
@W: toplevel.v(173): Input PHY_RX_CLK_ is unused @W:"u:\lab4\toplevel.v":173:18:173:88
@W: toplevel.v(174): Input PHY_RX_ER_ is unused @W:"u:\lab4\toplevel.v":174:18:174:28
@W: toplevel.v(176): Input PHY_TX_CLK_ is unused @W:"u:\lab4\toplevel.v":176:18:176:29
@W: toplevel.v(182): Input PHY_COL_ is unused @W:"u:\lab4\toplevel.v":182:18:182:26
@W: toplevel.v(183): Input PHY_CRS_ is unused @W:"u:\lab4\toplevel.v":183:18:183:26
@W: toplevel.v(187): Input AP_SDATA_OUT is unused @W:"u:\lab4\toplevel.v":187:19:187:31
@W: toplevel.v(188): Input AP_BIT_CLOCK is unused @W:"u:\lab4\toplevel.v":188:12:188:24
@W: toplevel.v(197): Inout RAM_DQ is unused @W:"u:\lab4\toplevel.v":197:17:197:23
@W: toplevel.v(214): Input ACE_MPBRDY is unused @W:"u:\lab4\toplevel.v":214:19:214:29
@W: toplevel.v(220): Inout ACE_MPD is unused @W:"u:\lab4\toplevel.v":220:18:220:25
@W: toplevel.v(224): Input VE_SCLK is unused @W:"u:\lab4\toplevel.v":224:12:224:19
@W: toplevel.v(226): Input VE_PAL_NTSC is unused @W:"u:\lab4\toplevel.v":226:12:226:23
@W: toplevel.v(228): Input VE_HSYNC_B is unused @W:"u:\lab4\toplevel.v":228:12:228:22
@W: toplevel.v(229): Input VE_VSYNC_B is unused @W:"u:\lab4\toplevel.v":229:12:229:22
@W: toplevel.v(230): Input VE_BLANK_B is unused @W:"u:\lab4\toplevel.v":230:12:230:22
@W: toplevel.v(236): Input VD_CLOCK is unused @W:"u:\lab4\toplevel.v":236:19:236:27
@W: toplevel.v(237): Input VD_CHAN1_LLC is unused @W:"u:\lab4\toplevel.v":237:18:237:30
@W: toplevel.v(238): Input VD_CHAN1_DATA is unused @W:"u:\lab4\toplevel.v":238:18:238:31
@W: toplevel.v(239): Input VD_CHAN1_I2C_CLOCK is unused @W:"u:\lab4\toplevel.v":239:12:239:30
@W: toplevel.v(240): Input VD_CHAN1_I2C_DATA is unused @W:"u:\lab4\toplevel.v":240:12:240:29
@W: toplevel.v(241): Input VD_CHAN1_ISO is unused @W:"u:\lab4\toplevel.v":241:12:241:24
194 Verilog Compiler warnings
@W: toplevel.v(225): tristate driver VE_SDA on net VE_SDA has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":225:13:225:19
@W: toplevel.v(231): tristate driver VE_SCRESET on net VE_SCRESET has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":231:13:231:23
@W: toplevel.v(227): tristate driver VE_RESET_B on net VE_RESET_B has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":227:13:227:23
@W: toplevel.v(223): tristate driver VE_P_10 on net VE_P_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_9 on net VE_P_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_8 on net VE_P_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_7 on net VE_P_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_6 on net VE_P_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_5 on net VE_P_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_4 on net VE_P_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_3 on net VE_P_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_2 on net VE_P_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_1 on net VE_P_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(233): tristate driver VE_CLKIN_ on net VE_CLKIN_ has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":233:13:233:22
@W: toplevel.v(242): tristate driver VD_RESET_B on net VD_RESET_B has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":242:13:242:23
@W: toplevel.v(298): tristate driver SEG_PT__8 on net SEG_PT__8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__7 on net SEG_PT__7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__6 on net SEG_PT__6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__5 on net SEG_PT__5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__4 on net SEG_PT__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__3 on net SEG_PT__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__2 on net SEG_PT__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__1 on net SEG_PT__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(143): tristate driver RJ45_TRC_2 on net RJ45_TRC_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":143:18:143:26
@W: toplevel.v(143): tristate driver RJ45_TRC_1 on net RJ45_TRC_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":143:18:143:26
@W: toplevel.v(145): tristate driver RJ45_TLC_2 on net RJ45_TLC_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":145:18:145:26
@W: toplevel.v(145): tristate driver RJ45_TLC_1 on net RJ45_TLC_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":145:18:145:26
@W: toplevel.v(144): tristate driver RJ45_BRC_2 on net RJ45_BRC_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":144:18:144:26
@W: toplevel.v(144): tristate driver RJ45_BRC_1 on net RJ45_BRC_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":144:18:144:26
@W: toplevel.v(146): tristate driver RJ45_BLC_2 on net RJ45_BLC_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":146:18:146:26
@W: toplevel.v(146): tristate driver RJ45_BLC_1 on net RJ45_BLC_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":146:18:146:26
@W: toplevel.v(205): tristate driver RAM_WE on net RAM_WE has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":205:19:205:25
@W: toplevel.v(203): tristate driver RAM_RAS on net RAM_RAS has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":203:19:203:26
@W: toplevel.v(201): tristate driver RAM_DQML on net RAM_DQML has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":201:19:201:27
@W: toplevel.v(200): tristate driver RAM_DQMH on net RAM_DQMH has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":200:19:200:27
@W: toplevel.v(202): tristate driver RAM_CS on net RAM_CS has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":202:19:202:25
@W: toplevel.v(199): tristate driver RAM_CLKE on net RAM_CLKE has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":199:19:199:27
@W: toplevel.v(198): tristate driver RAM_CLK on net RAM_CLK has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":198:19:198:26
@W: toplevel.v(204): tristate driver RAM_CAS on net RAM_CAS has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":204:19:204:26
@W: toplevel.v(206): tristate driver RAM_BA_2 on net RAM_BA_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":206:24:206:30
@W: toplevel.v(206): tristate driver RAM_BA_1 on net RAM_BA_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":206:24:206:30
@W: toplevel.v(207): tristate driver RAM_A_12 on net RAM_A_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_11 on net RAM_A_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_10 on net RAM_A_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_9 on net RAM_A_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_8 on net RAM_A_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_7 on net RAM_A_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_6 on net RAM_A_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_5 on net RAM_A_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_4 on net RAM_A_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_3 on net RAM_A_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_2 on net RAM_A_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_1 on net RAM_A_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_20 on net PINOUT_TOP_FAR_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_19 on net PINOUT_TOP_FAR_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_18 on net PINOUT_TOP_FAR_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_17 on net PINOUT_TOP_FAR_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_16 on net PINOUT_TOP_FAR_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_15 on net PINOUT_TOP_FAR_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_14 on net PINOUT_TOP_FAR_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_13 on net PINOUT_TOP_FAR_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_12 on net PINOUT_TOP_FAR_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_11 on net PINOUT_TOP_FAR_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_10 on net PINOUT_TOP_FAR_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_9 on net PINOUT_TOP_FAR_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_8 on net PINOUT_TOP_FAR_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_7 on net PINOUT_TOP_FAR_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_6 on net PINOUT_TOP_FAR_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_5 on net PINOUT_TOP_FAR_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_4 on net PINOUT_TOP_FAR_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_3 on net PINOUT_TOP_FAR_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_2 on net PINOUT_TOP_FAR_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_1 on net PINOUT_TOP_FAR_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_20 on net PINOUT_TOP_CLOSE_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_19 on net PINOUT_TOP_CLOSE_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_18 on net PINOUT_TOP_CLOSE_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_17 on net PINOUT_TOP_CLOSE_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_16 on net PINOUT_TOP_CLOSE_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_15 on net PINOUT_TOP_CLOSE_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_14 on net PINOUT_TOP_CLOSE_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_13 on net PINOUT_TOP_CLOSE_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_12 on net PINOUT_TOP_CLOSE_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_11 on net PINOUT_TOP_CLOSE_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_10 on net PINOUT_TOP_CLOSE_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_9 on net PINOUT_TOP_CLOSE_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_8 on net PINOUT_TOP_CLOSE_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_7 on net PINOUT_TOP_CLOSE_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_6 on net PINOUT_TOP_CLOSE_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_5 on net PINOUT_TOP_CLOSE_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_4 on net PINOUT_TOP_CLOSE_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_3 on net PINOUT_TOP_CLOSE_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_2 on net PINOUT_TOP_CLOSE_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_1 on net PINOUT_TOP_CLOSE_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_20 on net PINOUT_RIGHT_FAR_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_19 on net PINOUT_RIGHT_FAR_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_18 on net PINOUT_RIGHT_FAR_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_17 on net PINOUT_RIGHT_FAR_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_16 on net PINOUT_RIGHT_FAR_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_15 on net PINOUT_RIGHT_FAR_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_14 on net PINOUT_RIGHT_FAR_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_13 on net PINOUT_RIGHT_FAR_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_12 on net PINOUT_RIGHT_FAR_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_11 on net PINOUT_RIGHT_FAR_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_10 on net PINOUT_RIGHT_FAR_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_9 on net PINOUT_RIGHT_FAR_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_8 on net PINOUT_RIGHT_FAR_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_7 on net PINOUT_RIGHT_FAR_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_6 on net PINOUT_RIGHT_FAR_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_5 on net PINOUT_RIGHT_FAR_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_4 on net PINOUT_RIGHT_FAR_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_3 on net PINOUT_RIGHT_FAR_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_2 on net PINOUT_RIGHT_FAR_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_1 on net PINOUT_RIGHT_FAR_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_20 on net PINOUT_RIGHT_CLOSE_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_19 on net PINOUT_RIGHT_CLOSE_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_18 on net PINOUT_RIGHT_CLOSE_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_17 on net PINOUT_RIGHT_CLOSE_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_16 on net PINOUT_RIGHT_CLOSE_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_15 on net PINOUT_RIGHT_CLOSE_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_14 on net PINOUT_RIGHT_CLOSE_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_13 on net PINOUT_RIGHT_CLOSE_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_12 on net PINOUT_RIGHT_CLOSE_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_11 on net PINOUT_RIGHT_CLOSE_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_10 on net PINOUT_RIGHT_CLOSE_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_9 on net PINOUT_RIGHT_CLOSE_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_8 on net PINOUT_RIGHT_CLOSE_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_7 on net PINOUT_RIGHT_CLOSE_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_6 on net PINOUT_RIGHT_CLOSE_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_5 on net PINOUT_RIGHT_CLOSE_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_4 on net PINOUT_RIGHT_CLOSE_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_3 on net PINOUT_RIGHT_CLOSE_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_2 on net PINOUT_RIGHT_CLOSE_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_1 on net PINOUT_RIGHT_CLOSE_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_20 on net PINOUT_LEFT_FAR_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_19 on net PINOUT_LEFT_FAR_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_18 on net PINOUT_LEFT_FAR_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_17 on net PINOUT_LEFT_FAR_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_16 on net PINOUT_LEFT_FAR_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_15 on net PINOUT_LEFT_FAR_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_14 on net PINOUT_LEFT_FAR_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_13 on net PINOUT_LEFT_FAR_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_12 on net PINOUT_LEFT_FAR_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_11 on net PINOUT_LEFT_FAR_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_10 on net PINOUT_LEFT_FAR_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_9 on net PINOUT_LEFT_FAR_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_8 on net PINOUT_LEFT_FAR_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_7 on net PINOUT_LEFT_FAR_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_6 on net PINOUT_LEFT_FAR_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_5 on net PINOUT_LEFT_FAR_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_4 on net PINOUT_LEFT_FAR_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_3 on net PINOUT_LEFT_FAR_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_2 on net PINOUT_LEFT_FAR_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_1 on net PINOUT_LEFT_FAR_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_20 on net PINOUT_LEFT_CLOSE_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_19 on net PINOUT_LEFT_CLOSE_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_18 on net PINOUT_LEFT_CLOSE_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_17 on net PINOUT_LEFT_CLOSE_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_16 on net PINOUT_LEFT_CLOSE_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_15 on net PINOUT_LEFT_CLOSE_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_14 on net PINOUT_LEFT_CLOSE_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_13 on net PINOUT_LEFT_CLOSE_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_12 on net PINOUT_LEFT_CLOSE_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_11 on net PINOUT_LEFT_CLOSE_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_10 on net PINOUT_LEFT_CLOSE_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_9 on net PINOUT_LEFT_CLOSE_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_8 on net PINOUT_LEFT_CLOSE_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_7 on net PINOUT_LEFT_CLOSE_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_6 on net PINOUT_LEFT_CLOSE_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_5 on net PINOUT_LEFT_CLOSE_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_4 on net PINOUT_LEFT_CLOSE_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_3 on net PINOUT_LEFT_CLOSE_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_2 on net PINOUT_LEFT_CLOSE_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_1 on net PINOUT_LEFT_CLOSE_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_20 on net PINOUT_BOTTOM_FAR_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_19 on net PINOUT_BOTTOM_FAR_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_18 on net PINOUT_BOTTOM_FAR_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_17 on net PINOUT_BOTTOM_FAR_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_16 on net PINOUT_BOTTOM_FAR_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_15 on net PINOUT_BOTTOM_FAR_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_14 on net PINOUT_BOTTOM_FAR_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_13 on net PINOUT_BOTTOM_FAR_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_12 on net PINOUT_BOTTOM_FAR_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_11 on net PINOUT_BOTTOM_FAR_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_10 on net PINOUT_BOTTOM_FAR_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_9 on net PINOUT_BOTTOM_FAR_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_8 on net PINOUT_BOTTOM_FAR_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_7 on net PINOUT_BOTTOM_FAR_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_6 on net PINOUT_BOTTOM_FAR_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_5 on net PINOUT_BOTTOM_FAR_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_4 on net PINOUT_BOTTOM_FAR_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_3 on net PINOUT_BOTTOM_FAR_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_2 on net PINOUT_BOTTOM_FAR_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_1 on net PINOUT_BOTTOM_FAR_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_20 on net PINOUT_BOTTOM_CLOSE_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_19 on net PINOUT_BOTTOM_CLOSE_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_18 on net PINOUT_BOTTOM_CLOSE_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_17 on net PINOUT_BOTTOM_CLOSE_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_16 on net PINOUT_BOTTOM_CLOSE_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_15 on net PINOUT_BOTTOM_CLOSE_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_14 on net PINOUT_BOTTOM_CLOSE_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_13 on net PINOUT_BOTTOM_CLOSE_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_12 on net PINOUT_BOTTOM_CLOSE_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_11 on net PINOUT_BOTTOM_CLOSE_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_10 on net PINOUT_BOTTOM_CLOSE_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_9 on net PINOUT_BOTTOM_CLOSE_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_8 on net PINOUT_BOTTOM_CLOSE_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_7 on net PINOUT_BOTTOM_CLOSE_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_6 on net PINOUT_BOTTOM_CLOSE_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_5 on net PINOUT_BOTTOM_CLOSE_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_4 on net PINOUT_BOTTOM_CLOSE_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_3 on net PINOUT_BOTTOM_CLOSE_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_2 on net PINOUT_BOTTOM_CLOSE_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_1 on net PINOUT_BOTTOM_CLOSE_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(175): tristate driver PHY_TX_ER__4 on net PHY_TX_ER__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":175:18:175:28
@W: toplevel.v(175): tristate driver PHY_TX_ER__3 on net PHY_TX_ER__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":175:18:175:28
@W: toplevel.v(175): tristate driver PHY_TX_ER__2 on net PHY_TX_ER__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":175:18:175:28
@W: toplevel.v(175): tristate driver PHY_TX_ER__1 on net PHY_TX_ER__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":175:18:175:28
@W: toplevel.v(177): tristate driver PHY_TX_EN__4 on net PHY_TX_EN__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":177:18:177:28
@W: toplevel.v(177): tristate driver PHY_TX_EN__3 on net PHY_TX_EN__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":177:18:177:28
@W: toplevel.v(177): tristate driver PHY_TX_EN__2 on net PHY_TX_EN__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":177:18:177:28
@W: toplevel.v(177): tristate driver PHY_TX_EN__1 on net PHY_TX_EN__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":177:18:177:28
@W: toplevel.v(181): tristate driver PHY_TXD3__4 on net PHY_TXD3__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":181:18:181:27
@W: toplevel.v(181): tristate driver PHY_TXD3__3 on net PHY_TXD3__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":181:18:181:27
@W: toplevel.v(181): tristate driver PHY_TXD3__2 on net PHY_TXD3__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":181:18:181:27
@W: toplevel.v(181): tristate driver PHY_TXD3__1 on net PHY_TXD3__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":181:18:181:27
@W: toplevel.v(180): tristate driver PHY_TXD2__4 on net PHY_TXD2__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":180:18:180:27
@W: toplevel.v(180): tristate driver PHY_TXD2__3 on net PHY_TXD2__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":180:18:180:27
@W: toplevel.v(180): tristate driver PHY_TXD2__2 on net PHY_TXD2__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":180:18:180:27
@W: toplevel.v(180): tristate driver PHY_TXD2__1 on net PHY_TXD2__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":180:18:180:27
@W: toplevel.v(179): tristate driver PHY_TXD1__4 on net PHY_TXD1__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":179:18:179:27
@W: toplevel.v(179): tristate driver PHY_TXD1__3 on net PHY_TXD1__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":179:18:179:27
@W: toplevel.v(179): tristate driver PHY_TXD1__2 on net PHY_TXD1__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":179:18:179:27
@W: toplevel.v(179): tristate driver PHY_TXD1__1 on net PHY_TXD1__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":179:18:179:27
@W: toplevel.v(178): tristate driver PHY_TXD0__4 on net PHY_TXD0__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":178:18:178:27
@W: toplevel.v(178): tristate driver PHY_TXD0__3 on net PHY_TXD0__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":178:18:178:27
@W: toplevel.v(178): tristate driver PHY_TXD0__2 on net PHY_TXD0__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":178:18:178:27
@W: toplevel.v(178): tristate driver PHY_TXD0__1 on net PHY_TXD0__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":178:18:178:27
@W: toplevel.v(184): tristate driver PHY_TRSTE__4 on net PHY_TRSTE__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":184:18:184:28
@W: toplevel.v(184): tristate driver PHY_TRSTE__3 on net PHY_TRSTE__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":184:18:184:28
@W: toplevel.v(184): tristate driver PHY_TRSTE__2 on net PHY_TRSTE__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":184:18:184:28
@W: toplevel.v(184): tristate driver PHY_TRSTE__1 on net PHY_TRSTE__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":184:18:184:28
@W: toplevel.v(159): tristate driver PHY_RESET on net PHY_RESET has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":159:13:159:22
@W: toplevel.v(158): tristate driver PHY_PWRDN on net PHY_PWRDN has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":158:13:158:22
@W: toplevel.v(157): tristate driver PHY_MDDIS on net PHY_MDDIS has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":157:13:157:22
@W: toplevel.v(156): tristate driver PHY_MDC on net PHY_MDC has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":156:13:156:20
@W: toplevel.v(160): tristate driver PHY_FDE on net PHY_FDE has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":160:13:160:20
@W: toplevel.v(163): tristate driver PHY_CFG__3 on net PHY_CFG__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":163:18:163:26
@W: toplevel.v(163): tristate driver PHY_CFG__2 on net PHY_CFG__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":163:18:163:26
@W: toplevel.v(163): tristate driver PHY_CFG__1 on net PHY_CFG__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":163:18:163:26
@W: toplevel.v(162): tristate driver PHY_BYPSCR on net PHY_BYPSCR has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":162:13:162:23
@W: toplevel.v(161): tristate driver PHY_AUTOENA on net PHY_AUTOENA has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":161:13:161:24
@W: toplevel.v(152): tristate driver PHY_ADD__3 on net PHY_ADD__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":152:18:152:26
@W: toplevel.v(152): tristate driver PHY_ADD__2 on net PHY_ADD__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":152:18:152:26
@W: toplevel.v(152): tristate driver PHY_ADD__1 on net PHY_ADD__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":152:18:152:26
@W: toplevel.v(190): tristate driver AP_SYNC on net AP_SYNC has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":190:13:190:20
@W: toplevel.v(189): tristate driver AP_SDATA_IN on net AP_SDATA_IN has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":189:13:189:24
@W: toplevel.v(191): tristate driver AP_RESET_B on net AP_RESET_B has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":191:13:191:23
@W: toplevel.v(192): tristate driver AP_PC_BEEP on net AP_PC_BEEP has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":192:13:192:23
@W: toplevel.v(217): tristate driver ACE_MPWE_B on net ACE_MPWE_B has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":217:13:217:23
@W: toplevel.v(218): tristate driver ACE_MPOE_B on net ACE_MPOE_B has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":218:13:218:23
@W: toplevel.v(215): tristate driver ACE_MPIRQ on net ACE_MPIRQ has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":215:13:215:22
@W: toplevel.v(216): tristate driver ACE_MPCE_B on net ACE_MPCE_B has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":216:13:216:23
@W: toplevel.v(219): tristate driver ACE_MPA_7 on net ACE_MPA_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(219): tristate driver ACE_MPA_6 on net ACE_MPA_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(219): tristate driver ACE_MPA_5 on net ACE_MPA_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(219): tristate driver ACE_MPA_4 on net ACE_MPA_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(219): tristate driver ACE_MPA_3 on net ACE_MPA_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(219): tristate driver ACE_MPA_2 on net ACE_MPA_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(219): tristate driver ACE_MPA_1 on net ACE_MPA_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(194): tristate driver AA_MUTE on net AA_MUTE has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":194:13:194:20
270 VIRTEX-E Mapper warnings
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Anything generated by topLevel, dataBoardRam, instBoardRam is ok.
Everything else is an error.
@W: databoardram.v(58): No assignment to memoryLines_0_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_1_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_2_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_3_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_4_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_5_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_6_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_7_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_8_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_9_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_10_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_11_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_12_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_13_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_14_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_15_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_16_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_17_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_18_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_19_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_20_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_21_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_22_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_23_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_24_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_25_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_26_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_27_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_28_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_29_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_30_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_31_ @W:"u:\lab4\databoardram.v":58:11:58:22
@W: databoardram.v(60): No assignment to tempcount @W:"u:\lab4\databoardram.v":60:4:60:13
@W: hazarddetect.v(43): Input break is unused @W:"u:\lab4\hazarddetect.v":43:8:43:13
@W: instboardram.v(58): No assignment to memoryLines_0_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_1_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_2_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_3_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_4_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_5_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_6_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_7_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_8_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_9_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_10_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_11_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_12_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_13_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_14_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_15_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_16_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_17_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_18_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_19_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_20_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_21_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_22_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_23_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_24_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_25_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_26_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_27_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_28_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_29_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_30_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(58): No assignment to memoryLines_31_ @W:"u:\lab4\instboardram.v":58:11:58:22
@W: instboardram.v(60): No assignment to tempcount @W:"u:\lab4\instboardram.v":60:4:60:13
@W: instmem.v(16): Port width mismatch for port we. Formal has width 1, Actual 32 @W:"u:\lab4\instmem.v":16:52:16:57
@W: mux4.v(15): Incomplete sensitivity list - assuming completeness @W:"u:\lab4\mux4.v":15:13:15:37
@W: mux4.v(21): Referenced variable in3 is not in sensitivity list @W:"u:\lab4\mux4.v":21:13:21:16
@W: regfile.v(27): Register 'file_0_' is only assigned 0 or its old value; the register will be removed @W:"u:\lab4\regfile.v":27:0:27:6
@W: shifter.v(11): Input logical is unused @W:"u:\lab4\shifter.v":11:22:11:29
@W: monitor.v(96): Ignoring initial statement @W:"u:\lab4\monitor.v":96:3:96:10
@W: monitor.v(13): Input clk is unused @W:"u:\lab4\monitor.v":13:9:13:12
@W: monitor.v(14): Input address is unused @W:"u:\lab4\monitor.v":14:16:14:23
@W: monitor.v(15): Input instruction is unused @W:"u:\lab4\monitor.v":15:2:15:13
@W: monitor.v(16): Input memOutput is unused @W:"u:\lab4\monitor.v":16:2:16:11
@W: monitor.v(17): Input regOutA is unused @W:"u:\lab4\monitor.v":17:2:17:9
@W: monitor.v(18): Input regOutB is unused @W:"u:\lab4\monitor.v":18:2:18:9
@W: monitor.v(19): Input aluOut is unused @W:"u:\lab4\monitor.v":19:2:19:8
@W: monitor.v(20): Input nextPc is unused @W:"u:\lab4\monitor.v":20:9:20:15
@W: monitor.v(22): Input stall is unused @W:"u:\lab4\monitor.v":22:10:22:15
@W: cpu.v(225): Undriven input idBranch, tying to 0 @W:"u:\lab4\cpu.v":225:69:225:77
@W: cpu.v(225): Undriven input idPcSrc, tying to 0 @W:"u:\lab4\cpu.v":225:81:225:88
@W: cpu.v(226): Undriven input exJal, tying to 0 @W:"u:\lab4\cpu.v":226:4:226:9
@W: cpu.v(226): Undriven input exLui, tying to 0 @W:"u:\lab4\cpu.v":226:35:226:40
@W: cpu.v(227): Undriven input memMemToReg, tying to 0 @W:"u:\lab4\cpu.v":227:4:227:15
@W: cpu.v(227): Undriven input wbRw, tying to 0 @W:"u:\lab4\cpu.v":227:20:227:24
@W: cpu.v(227): Undriven input wbRegWr, tying to 0 @W:"u:\lab4\cpu.v":227:29:227:36
@W: cpu.v(253): Undriven input idAluSrc, tying to 0 @W:"u:\lab4\cpu.v":253:24:253:32
@W: cpu.v(253): Undriven input idMemWrEnb, tying to 0 @W:"u:\lab4\cpu.v":253:37:253:47
@W: cpu.v(253): Undriven input idBranch, tying to 0 @W:"u:\lab4\cpu.v":253:52:253:60
@W: cpu.v(253): Undriven input idBez, tying to 0 @W:"u:\lab4\cpu.v":253:65:253:70
@W: cpu.v(255): Undriven input idPcSrc, tying to 0 @W:"u:\lab4\cpu.v":255:7:255:14
@W: cpu.v(255): Undriven input exRegWrEnb, tying to 0 @W:"u:\lab4\cpu.v":255:19:255:29
@W: cpu.v(255): Undriven input exMemToReg, tying to 0 @W:"u:\lab4\cpu.v":255:34:255:44
@W: cpu.v(255): Undriven input exCoProc, tying to 0 @W:"u:\lab4\cpu.v":255:49:255:57
@W: cpu.v(255): Undriven input memMemToReg, tying to 0 @W:"u:\lab4\cpu.v":255:62:255:73
@W: cpu.v(257): Undriven input break, tying to 0 @W:"u:\lab4\cpu.v":257:41:257:46
@W: cpu.v(257): Undriven input idRs, tying to 0 @W:"u:\lab4\cpu.v":257:51:257:55
@W: cpu.v(257): Undriven input idRt, tying to 0 @W:"u:\lab4\cpu.v":257:60:257:64
@W: cpu.v(257): Undriven input exRw, tying to 0 @W:"u:\lab4\cpu.v":257:69:257:73
@W: cpu.v(259): Undriven input memRw, tying to 0 @W:"u:\lab4\cpu.v":259:7:259:12
@W: processor.v(21): Port width mismatch for port stat. Formal has width 7, Actual 8 @W:"u:\lab4\processor.v":21:66:21:70
@W: toplevel.v(143): *Output RJ45_TRC has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":143:18:143:26
@W: toplevel.v(144): *Output RJ45_BRC has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":144:18:144:26
@W: toplevel.v(145): *Output RJ45_TLC has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":145:18:145:26
@W: toplevel.v(146): *Output RJ45_BLC has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":146:18:146:26
@W: toplevel.v(152): *Output PHY_ADD_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":152:18:152:26
@W: toplevel.v(156): *Output PHY_MDC has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":156:13:156:20
@W: toplevel.v(157): *Output PHY_MDDIS has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":157:13:157:22
@W: toplevel.v(158): *Output PHY_PWRDN has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":158:13:158:22
@W: toplevel.v(159): *Output PHY_RESET has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":159:13:159:22
@W: toplevel.v(160): *Output PHY_FDE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":160:13:160:20
@W: toplevel.v(161): *Output PHY_AUTOENA has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":161:13:161:24
@W: toplevel.v(162): *Output PHY_BYPSCR has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":162:13:162:23
@W: toplevel.v(163): *Output PHY_CFG_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":163:18:163:26
@W: toplevel.v(175): *Output PHY_TX_ER_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":175:18:175:28
@W: toplevel.v(177): *Output PHY_TX_EN_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":177:18:177:28
@W: toplevel.v(178): *Output PHY_TXD0_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":178:18:178:27
@W: toplevel.v(179): *Output PHY_TXD1_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":179:18:179:27
@W: toplevel.v(180): *Output PHY_TXD2_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":180:18:180:27
@W: toplevel.v(181): *Output PHY_TXD3_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":181:18:181:27
@W: toplevel.v(184): *Output PHY_TRSTE_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":184:18:184:28
@W: toplevel.v(189): *Output AP_SDATA_IN has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":189:13:189:24
@W: toplevel.v(190): *Output AP_SYNC has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":190:13:190:20
@W: toplevel.v(191): *Output AP_RESET_B has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":191:13:191:23
@W: toplevel.v(192): *Output AP_PC_BEEP has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":192:13:192:23
@W: toplevel.v(194): *Output AA_MUTE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":194:13:194:20
@W: toplevel.v(198): *Output RAM_CLK has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":198:19:198:26
@W: toplevel.v(199): *Output RAM_CLKE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":199:19:199:27
@W: toplevel.v(200): *Output RAM_DQMH has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":200:19:200:27
@W: toplevel.v(201): *Output RAM_DQML has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":201:19:201:27
@W: toplevel.v(202): *Output RAM_CS has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":202:19:202:25
@W: toplevel.v(203): *Output RAM_RAS has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":203:19:203:26
@W: toplevel.v(204): *Output RAM_CAS has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":204:19:204:26
@W: toplevel.v(205): *Output RAM_WE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":205:19:205:25
@W: toplevel.v(206): *Output RAM_BA has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":206:24:206:30
@W: toplevel.v(207): *Output RAM_A has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(215): *Output ACE_MPIRQ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":215:13:215:22
@W: toplevel.v(216): *Output ACE_MPCE_B has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":216:13:216:23
@W: toplevel.v(217): *Output ACE_MPWE_B has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":217:13:217:23
@W: toplevel.v(218): *Output ACE_MPOE_B has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":218:13:218:23
@W: toplevel.v(219): *Output ACE_MPA has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(223): *Output VE_P has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(225): *Output VE_SDA has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":225:13:225:19
@W: toplevel.v(227): *Output VE_RESET_B has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":227:13:227:23
@W: toplevel.v(231): *Output VE_SCRESET has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":231:13:231:23
@W: toplevel.v(233): *Output VE_CLKIN_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":233:13:233:22
@W: toplevel.v(242): *Output VD_RESET_B has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":242:13:242:23
@W: toplevel.v(298): *Output SEG_PT_ has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(259): *Output PINOUT_TOP_CLOSE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(260): *Output PINOUT_TOP_FAR has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(261): *Output PINOUT_LEFT_CLOSE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(262): *Output PINOUT_LEFT_FAR has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(263): *Output PINOUT_BOTTOM_CLOSE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(264): *Output PINOUT_BOTTOM_FAR has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(265): *Output PINOUT_RIGHT_CLOSE has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(266): *Output PINOUT_RIGHT_FAR has undriven bits - a simulation mismatch is possible @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(149): Input PHY_LEDCLK is unused @W:"u:\lab4\toplevel.v":149:11:149:21
@W: toplevel.v(150): Input PHY_LEDDAT is unused @W:"u:\lab4\toplevel.v":150:12:150:22
@W: toplevel.v(151): Input PHY_LEDENA is unused @W:"u:\lab4\toplevel.v":151:12:151:22
@W: toplevel.v(154): Input PHY_MDIO is unused @W:"u:\lab4\toplevel.v":154:12:154:20
@W: toplevel.v(155): Input PHY_MDINT is unused @W:"u:\lab4\toplevel.v":155:12:155:21
@W: toplevel.v(164): Input PHY_LED0_ is unused @W:"u:\lab4\toplevel.v":164:18:164:27
@W: toplevel.v(165): Input PHY_LED1_ is unused @W:"u:\lab4\toplevel.v":165:18:165:27
@W: toplevel.v(166): Input PHY_LED2_ is unused @W:"u:\lab4\toplevel.v":166:18:166:27
@W: toplevel.v(167): Input PHY_LED3_ is unused @W:"u:\lab4\toplevel.v":167:18:167:27
@W: toplevel.v(168): Input PHY_RXD0_ is unused @W:"u:\lab4\toplevel.v":168:18:168:27
@W: toplevel.v(169): Input PHY_RXD1_ is unused @W:"u:\lab4\toplevel.v":169:18:169:27
@W: toplevel.v(170): Input PHY_RXD2_ is unused @W:"u:\lab4\toplevel.v":170:18:170:27
@W: toplevel.v(171): Input PHY_RXD3_ is unused @W:"u:\lab4\toplevel.v":171:18:171:27
@W: toplevel.v(172): Input PHY_RX_DV_ is unused @W:"u:\lab4\toplevel.v":172:18:172:28
@W: toplevel.v(173): Input PHY_RX_CLK_ is unused @W:"u:\lab4\toplevel.v":173:18:173:88
@W: toplevel.v(174): Input PHY_RX_ER_ is unused @W:"u:\lab4\toplevel.v":174:18:174:28
@W: toplevel.v(176): Input PHY_TX_CLK_ is unused @W:"u:\lab4\toplevel.v":176:18:176:29
@W: toplevel.v(182): Input PHY_COL_ is unused @W:"u:\lab4\toplevel.v":182:18:182:26
@W: toplevel.v(183): Input PHY_CRS_ is unused @W:"u:\lab4\toplevel.v":183:18:183:26
@W: toplevel.v(187): Input AP_SDATA_OUT is unused @W:"u:\lab4\toplevel.v":187:19:187:31
@W: toplevel.v(188): Input AP_BIT_CLOCK is unused @W:"u:\lab4\toplevel.v":188:12:188:24
@W: toplevel.v(197): Inout RAM_DQ is unused @W:"u:\lab4\toplevel.v":197:17:197:23
@W: toplevel.v(214): Input ACE_MPBRDY is unused @W:"u:\lab4\toplevel.v":214:19:214:29
@W: toplevel.v(220): Inout ACE_MPD is unused @W:"u:\lab4\toplevel.v":220:18:220:25
@W: toplevel.v(224): Input VE_SCLK is unused @W:"u:\lab4\toplevel.v":224:12:224:19
@W: toplevel.v(226): Input VE_PAL_NTSC is unused @W:"u:\lab4\toplevel.v":226:12:226:23
@W: toplevel.v(228): Input VE_HSYNC_B is unused @W:"u:\lab4\toplevel.v":228:12:228:22
@W: toplevel.v(229): Input VE_VSYNC_B is unused @W:"u:\lab4\toplevel.v":229:12:229:22
@W: toplevel.v(230): Input VE_BLANK_B is unused @W:"u:\lab4\toplevel.v":230:12:230:22
@W: toplevel.v(236): Input VD_CLOCK is unused @W:"u:\lab4\toplevel.v":236:19:236:27
@W: toplevel.v(237): Input VD_CHAN1_LLC is unused @W:"u:\lab4\toplevel.v":237:18:237:30
@W: toplevel.v(238): Input VD_CHAN1_DATA is unused @W:"u:\lab4\toplevel.v":238:18:238:31
@W: toplevel.v(239): Input VD_CHAN1_I2C_CLOCK is unused @W:"u:\lab4\toplevel.v":239:12:239:30
@W: toplevel.v(240): Input VD_CHAN1_I2C_DATA is unused @W:"u:\lab4\toplevel.v":240:12:240:29
@W: toplevel.v(241): Input VD_CHAN1_ISO is unused @W:"u:\lab4\toplevel.v":241:12:241:24
194 Verilog Compiler warnings
@W: toplevel.v(225): tristate driver VE_SDA on net VE_SDA has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":225:13:225:19
@W: toplevel.v(231): tristate driver VE_SCRESET on net VE_SCRESET has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":231:13:231:23
@W: toplevel.v(227): tristate driver VE_RESET_B on net VE_RESET_B has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":227:13:227:23
@W: toplevel.v(223): tristate driver VE_P_10 on net VE_P_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_9 on net VE_P_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_8 on net VE_P_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_7 on net VE_P_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_6 on net VE_P_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_5 on net VE_P_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_4 on net VE_P_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_3 on net VE_P_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_2 on net VE_P_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(223): tristate driver VE_P_1 on net VE_P_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":223:25:223:29
@W: toplevel.v(233): tristate driver VE_CLKIN_ on net VE_CLKIN_ has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":233:13:233:22
@W: toplevel.v(242): tristate driver VD_RESET_B on net VD_RESET_B has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":242:13:242:23
@W: toplevel.v(298): tristate driver SEG_PT__8 on net SEG_PT__8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__7 on net SEG_PT__7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__6 on net SEG_PT__6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__5 on net SEG_PT__5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__4 on net SEG_PT__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__3 on net SEG_PT__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__2 on net SEG_PT__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(298): tristate driver SEG_PT__1 on net SEG_PT__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":298:17:298:23
@W: toplevel.v(143): tristate driver RJ45_TRC_2 on net RJ45_TRC_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":143:18:143:26
@W: toplevel.v(143): tristate driver RJ45_TRC_1 on net RJ45_TRC_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":143:18:143:26
@W: toplevel.v(145): tristate driver RJ45_TLC_2 on net RJ45_TLC_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":145:18:145:26
@W: toplevel.v(145): tristate driver RJ45_TLC_1 on net RJ45_TLC_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":145:18:145:26
@W: toplevel.v(144): tristate driver RJ45_BRC_2 on net RJ45_BRC_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":144:18:144:26
@W: toplevel.v(144): tristate driver RJ45_BRC_1 on net RJ45_BRC_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":144:18:144:26
@W: toplevel.v(146): tristate driver RJ45_BLC_2 on net RJ45_BLC_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":146:18:146:26
@W: toplevel.v(146): tristate driver RJ45_BLC_1 on net RJ45_BLC_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":146:18:146:26
@W: toplevel.v(205): tristate driver RAM_WE on net RAM_WE has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":205:19:205:25
@W: toplevel.v(203): tristate driver RAM_RAS on net RAM_RAS has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":203:19:203:26
@W: toplevel.v(201): tristate driver RAM_DQML on net RAM_DQML has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":201:19:201:27
@W: toplevel.v(200): tristate driver RAM_DQMH on net RAM_DQMH has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":200:19:200:27
@W: toplevel.v(202): tristate driver RAM_CS on net RAM_CS has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":202:19:202:25
@W: toplevel.v(199): tristate driver RAM_CLKE on net RAM_CLKE has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":199:19:199:27
@W: toplevel.v(198): tristate driver RAM_CLK on net RAM_CLK has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":198:19:198:26
@W: toplevel.v(204): tristate driver RAM_CAS on net RAM_CAS has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":204:19:204:26
@W: toplevel.v(206): tristate driver RAM_BA_2 on net RAM_BA_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":206:24:206:30
@W: toplevel.v(206): tristate driver RAM_BA_1 on net RAM_BA_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":206:24:206:30
@W: toplevel.v(207): tristate driver RAM_A_12 on net RAM_A_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_11 on net RAM_A_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_10 on net RAM_A_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_9 on net RAM_A_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_8 on net RAM_A_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_7 on net RAM_A_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_6 on net RAM_A_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_5 on net RAM_A_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_4 on net RAM_A_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_3 on net RAM_A_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_2 on net RAM_A_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(207): tristate driver RAM_A_1 on net RAM_A_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":207:25:207:30
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_20 on net PINOUT_TOP_FAR_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_19 on net PINOUT_TOP_FAR_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_18 on net PINOUT_TOP_FAR_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_17 on net PINOUT_TOP_FAR_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_16 on net PINOUT_TOP_FAR_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_15 on net PINOUT_TOP_FAR_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_14 on net PINOUT_TOP_FAR_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_13 on net PINOUT_TOP_FAR_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_12 on net PINOUT_TOP_FAR_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_11 on net PINOUT_TOP_FAR_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_10 on net PINOUT_TOP_FAR_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_9 on net PINOUT_TOP_FAR_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_8 on net PINOUT_TOP_FAR_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_7 on net PINOUT_TOP_FAR_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_6 on net PINOUT_TOP_FAR_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_5 on net PINOUT_TOP_FAR_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_4 on net PINOUT_TOP_FAR_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_3 on net PINOUT_TOP_FAR_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_2 on net PINOUT_TOP_FAR_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(260): tristate driver PINOUT_TOP_FAR_1 on net PINOUT_TOP_FAR_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":260:18:260:32
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_20 on net PINOUT_TOP_CLOSE_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_19 on net PINOUT_TOP_CLOSE_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_18 on net PINOUT_TOP_CLOSE_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_17 on net PINOUT_TOP_CLOSE_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_16 on net PINOUT_TOP_CLOSE_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_15 on net PINOUT_TOP_CLOSE_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_14 on net PINOUT_TOP_CLOSE_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_13 on net PINOUT_TOP_CLOSE_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_12 on net PINOUT_TOP_CLOSE_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_11 on net PINOUT_TOP_CLOSE_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_10 on net PINOUT_TOP_CLOSE_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_9 on net PINOUT_TOP_CLOSE_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_8 on net PINOUT_TOP_CLOSE_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_7 on net PINOUT_TOP_CLOSE_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_6 on net PINOUT_TOP_CLOSE_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_5 on net PINOUT_TOP_CLOSE_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_4 on net PINOUT_TOP_CLOSE_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_3 on net PINOUT_TOP_CLOSE_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_2 on net PINOUT_TOP_CLOSE_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(259): tristate driver PINOUT_TOP_CLOSE_1 on net PINOUT_TOP_CLOSE_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":259:18:259:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_20 on net PINOUT_RIGHT_FAR_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_19 on net PINOUT_RIGHT_FAR_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_18 on net PINOUT_RIGHT_FAR_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_17 on net PINOUT_RIGHT_FAR_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_16 on net PINOUT_RIGHT_FAR_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_15 on net PINOUT_RIGHT_FAR_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_14 on net PINOUT_RIGHT_FAR_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_13 on net PINOUT_RIGHT_FAR_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_12 on net PINOUT_RIGHT_FAR_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_11 on net PINOUT_RIGHT_FAR_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_10 on net PINOUT_RIGHT_FAR_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_9 on net PINOUT_RIGHT_FAR_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_8 on net PINOUT_RIGHT_FAR_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_7 on net PINOUT_RIGHT_FAR_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_6 on net PINOUT_RIGHT_FAR_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_5 on net PINOUT_RIGHT_FAR_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_4 on net PINOUT_RIGHT_FAR_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_3 on net PINOUT_RIGHT_FAR_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_2 on net PINOUT_RIGHT_FAR_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(266): tristate driver PINOUT_RIGHT_FAR_1 on net PINOUT_RIGHT_FAR_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":266:18:266:34
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_20 on net PINOUT_RIGHT_CLOSE_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_19 on net PINOUT_RIGHT_CLOSE_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_18 on net PINOUT_RIGHT_CLOSE_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_17 on net PINOUT_RIGHT_CLOSE_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_16 on net PINOUT_RIGHT_CLOSE_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_15 on net PINOUT_RIGHT_CLOSE_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_14 on net PINOUT_RIGHT_CLOSE_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_13 on net PINOUT_RIGHT_CLOSE_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_12 on net PINOUT_RIGHT_CLOSE_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_11 on net PINOUT_RIGHT_CLOSE_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_10 on net PINOUT_RIGHT_CLOSE_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_9 on net PINOUT_RIGHT_CLOSE_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_8 on net PINOUT_RIGHT_CLOSE_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_7 on net PINOUT_RIGHT_CLOSE_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_6 on net PINOUT_RIGHT_CLOSE_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_5 on net PINOUT_RIGHT_CLOSE_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_4 on net PINOUT_RIGHT_CLOSE_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_3 on net PINOUT_RIGHT_CLOSE_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_2 on net PINOUT_RIGHT_CLOSE_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(265): tristate driver PINOUT_RIGHT_CLOSE_1 on net PINOUT_RIGHT_CLOSE_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":265:18:265:36
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_20 on net PINOUT_LEFT_FAR_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_19 on net PINOUT_LEFT_FAR_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_18 on net PINOUT_LEFT_FAR_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_17 on net PINOUT_LEFT_FAR_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_16 on net PINOUT_LEFT_FAR_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_15 on net PINOUT_LEFT_FAR_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_14 on net PINOUT_LEFT_FAR_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_13 on net PINOUT_LEFT_FAR_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_12 on net PINOUT_LEFT_FAR_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_11 on net PINOUT_LEFT_FAR_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_10 on net PINOUT_LEFT_FAR_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_9 on net PINOUT_LEFT_FAR_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_8 on net PINOUT_LEFT_FAR_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_7 on net PINOUT_LEFT_FAR_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_6 on net PINOUT_LEFT_FAR_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_5 on net PINOUT_LEFT_FAR_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_4 on net PINOUT_LEFT_FAR_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_3 on net PINOUT_LEFT_FAR_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_2 on net PINOUT_LEFT_FAR_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(262): tristate driver PINOUT_LEFT_FAR_1 on net PINOUT_LEFT_FAR_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":262:18:262:33
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_20 on net PINOUT_LEFT_CLOSE_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_19 on net PINOUT_LEFT_CLOSE_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_18 on net PINOUT_LEFT_CLOSE_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_17 on net PINOUT_LEFT_CLOSE_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_16 on net PINOUT_LEFT_CLOSE_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_15 on net PINOUT_LEFT_CLOSE_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_14 on net PINOUT_LEFT_CLOSE_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_13 on net PINOUT_LEFT_CLOSE_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_12 on net PINOUT_LEFT_CLOSE_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_11 on net PINOUT_LEFT_CLOSE_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_10 on net PINOUT_LEFT_CLOSE_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_9 on net PINOUT_LEFT_CLOSE_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_8 on net PINOUT_LEFT_CLOSE_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_7 on net PINOUT_LEFT_CLOSE_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_6 on net PINOUT_LEFT_CLOSE_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_5 on net PINOUT_LEFT_CLOSE_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_4 on net PINOUT_LEFT_CLOSE_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_3 on net PINOUT_LEFT_CLOSE_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_2 on net PINOUT_LEFT_CLOSE_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(261): tristate driver PINOUT_LEFT_CLOSE_1 on net PINOUT_LEFT_CLOSE_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":261:18:261:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_20 on net PINOUT_BOTTOM_FAR_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_19 on net PINOUT_BOTTOM_FAR_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_18 on net PINOUT_BOTTOM_FAR_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_17 on net PINOUT_BOTTOM_FAR_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_16 on net PINOUT_BOTTOM_FAR_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_15 on net PINOUT_BOTTOM_FAR_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_14 on net PINOUT_BOTTOM_FAR_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_13 on net PINOUT_BOTTOM_FAR_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_12 on net PINOUT_BOTTOM_FAR_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_11 on net PINOUT_BOTTOM_FAR_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_10 on net PINOUT_BOTTOM_FAR_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_9 on net PINOUT_BOTTOM_FAR_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_8 on net PINOUT_BOTTOM_FAR_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_7 on net PINOUT_BOTTOM_FAR_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_6 on net PINOUT_BOTTOM_FAR_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_5 on net PINOUT_BOTTOM_FAR_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_4 on net PINOUT_BOTTOM_FAR_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_3 on net PINOUT_BOTTOM_FAR_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_2 on net PINOUT_BOTTOM_FAR_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(264): tristate driver PINOUT_BOTTOM_FAR_1 on net PINOUT_BOTTOM_FAR_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":264:18:264:35
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_20 on net PINOUT_BOTTOM_CLOSE_20 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_19 on net PINOUT_BOTTOM_CLOSE_19 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_18 on net PINOUT_BOTTOM_CLOSE_18 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_17 on net PINOUT_BOTTOM_CLOSE_17 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_16 on net PINOUT_BOTTOM_CLOSE_16 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_15 on net PINOUT_BOTTOM_CLOSE_15 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_14 on net PINOUT_BOTTOM_CLOSE_14 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_13 on net PINOUT_BOTTOM_CLOSE_13 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_12 on net PINOUT_BOTTOM_CLOSE_12 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_11 on net PINOUT_BOTTOM_CLOSE_11 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_10 on net PINOUT_BOTTOM_CLOSE_10 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_9 on net PINOUT_BOTTOM_CLOSE_9 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_8 on net PINOUT_BOTTOM_CLOSE_8 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_7 on net PINOUT_BOTTOM_CLOSE_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_6 on net PINOUT_BOTTOM_CLOSE_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_5 on net PINOUT_BOTTOM_CLOSE_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_4 on net PINOUT_BOTTOM_CLOSE_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_3 on net PINOUT_BOTTOM_CLOSE_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_2 on net PINOUT_BOTTOM_CLOSE_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(263): tristate driver PINOUT_BOTTOM_CLOSE_1 on net PINOUT_BOTTOM_CLOSE_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":263:18:263:37
@W: toplevel.v(175): tristate driver PHY_TX_ER__4 on net PHY_TX_ER__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":175:18:175:28
@W: toplevel.v(175): tristate driver PHY_TX_ER__3 on net PHY_TX_ER__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":175:18:175:28
@W: toplevel.v(175): tristate driver PHY_TX_ER__2 on net PHY_TX_ER__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":175:18:175:28
@W: toplevel.v(175): tristate driver PHY_TX_ER__1 on net PHY_TX_ER__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":175:18:175:28
@W: toplevel.v(177): tristate driver PHY_TX_EN__4 on net PHY_TX_EN__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":177:18:177:28
@W: toplevel.v(177): tristate driver PHY_TX_EN__3 on net PHY_TX_EN__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":177:18:177:28
@W: toplevel.v(177): tristate driver PHY_TX_EN__2 on net PHY_TX_EN__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":177:18:177:28
@W: toplevel.v(177): tristate driver PHY_TX_EN__1 on net PHY_TX_EN__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":177:18:177:28
@W: toplevel.v(181): tristate driver PHY_TXD3__4 on net PHY_TXD3__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":181:18:181:27
@W: toplevel.v(181): tristate driver PHY_TXD3__3 on net PHY_TXD3__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":181:18:181:27
@W: toplevel.v(181): tristate driver PHY_TXD3__2 on net PHY_TXD3__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":181:18:181:27
@W: toplevel.v(181): tristate driver PHY_TXD3__1 on net PHY_TXD3__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":181:18:181:27
@W: toplevel.v(180): tristate driver PHY_TXD2__4 on net PHY_TXD2__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":180:18:180:27
@W: toplevel.v(180): tristate driver PHY_TXD2__3 on net PHY_TXD2__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":180:18:180:27
@W: toplevel.v(180): tristate driver PHY_TXD2__2 on net PHY_TXD2__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":180:18:180:27
@W: toplevel.v(180): tristate driver PHY_TXD2__1 on net PHY_TXD2__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":180:18:180:27
@W: toplevel.v(179): tristate driver PHY_TXD1__4 on net PHY_TXD1__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":179:18:179:27
@W: toplevel.v(179): tristate driver PHY_TXD1__3 on net PHY_TXD1__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":179:18:179:27
@W: toplevel.v(179): tristate driver PHY_TXD1__2 on net PHY_TXD1__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":179:18:179:27
@W: toplevel.v(179): tristate driver PHY_TXD1__1 on net PHY_TXD1__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":179:18:179:27
@W: toplevel.v(178): tristate driver PHY_TXD0__4 on net PHY_TXD0__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":178:18:178:27
@W: toplevel.v(178): tristate driver PHY_TXD0__3 on net PHY_TXD0__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":178:18:178:27
@W: toplevel.v(178): tristate driver PHY_TXD0__2 on net PHY_TXD0__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":178:18:178:27
@W: toplevel.v(178): tristate driver PHY_TXD0__1 on net PHY_TXD0__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":178:18:178:27
@W: toplevel.v(184): tristate driver PHY_TRSTE__4 on net PHY_TRSTE__4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":184:18:184:28
@W: toplevel.v(184): tristate driver PHY_TRSTE__3 on net PHY_TRSTE__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":184:18:184:28
@W: toplevel.v(184): tristate driver PHY_TRSTE__2 on net PHY_TRSTE__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":184:18:184:28
@W: toplevel.v(184): tristate driver PHY_TRSTE__1 on net PHY_TRSTE__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":184:18:184:28
@W: toplevel.v(159): tristate driver PHY_RESET on net PHY_RESET has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":159:13:159:22
@W: toplevel.v(158): tristate driver PHY_PWRDN on net PHY_PWRDN has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":158:13:158:22
@W: toplevel.v(157): tristate driver PHY_MDDIS on net PHY_MDDIS has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":157:13:157:22
@W: toplevel.v(156): tristate driver PHY_MDC on net PHY_MDC has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":156:13:156:20
@W: toplevel.v(160): tristate driver PHY_FDE on net PHY_FDE has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":160:13:160:20
@W: toplevel.v(163): tristate driver PHY_CFG__3 on net PHY_CFG__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":163:18:163:26
@W: toplevel.v(163): tristate driver PHY_CFG__2 on net PHY_CFG__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":163:18:163:26
@W: toplevel.v(163): tristate driver PHY_CFG__1 on net PHY_CFG__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":163:18:163:26
@W: toplevel.v(162): tristate driver PHY_BYPSCR on net PHY_BYPSCR has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":162:13:162:23
@W: toplevel.v(161): tristate driver PHY_AUTOENA on net PHY_AUTOENA has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":161:13:161:24
@W: toplevel.v(152): tristate driver PHY_ADD__3 on net PHY_ADD__3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":152:18:152:26
@W: toplevel.v(152): tristate driver PHY_ADD__2 on net PHY_ADD__2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":152:18:152:26
@W: toplevel.v(152): tristate driver PHY_ADD__1 on net PHY_ADD__1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":152:18:152:26
@W: toplevel.v(190): tristate driver AP_SYNC on net AP_SYNC has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":190:13:190:20
@W: toplevel.v(189): tristate driver AP_SDATA_IN on net AP_SDATA_IN has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":189:13:189:24
@W: toplevel.v(191): tristate driver AP_RESET_B on net AP_RESET_B has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":191:13:191:23
@W: toplevel.v(192): tristate driver AP_PC_BEEP on net AP_PC_BEEP has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":192:13:192:23
@W: toplevel.v(217): tristate driver ACE_MPWE_B on net ACE_MPWE_B has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":217:13:217:23
@W: toplevel.v(218): tristate driver ACE_MPOE_B on net ACE_MPOE_B has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":218:13:218:23
@W: toplevel.v(215): tristate driver ACE_MPIRQ on net ACE_MPIRQ has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":215:13:215:22
@W: toplevel.v(216): tristate driver ACE_MPCE_B on net ACE_MPCE_B has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":216:13:216:23
@W: toplevel.v(219): tristate driver ACE_MPA_7 on net ACE_MPA_7 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(219): tristate driver ACE_MPA_6 on net ACE_MPA_6 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(219): tristate driver ACE_MPA_5 on net ACE_MPA_5 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(219): tristate driver ACE_MPA_4 on net ACE_MPA_4 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(219): tristate driver ACE_MPA_3 on net ACE_MPA_3 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(219): tristate driver ACE_MPA_2 on net ACE_MPA_2 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(219): tristate driver ACE_MPA_1 on net ACE_MPA_1 has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":219:18:219:25
@W: toplevel.v(194): tristate driver AA_MUTE on net AA_MUTE has its enable tied to GND (module TopLevel) @W:"u:\lab4\toplevel.v":194:13:194:20
270 VIRTEX-E Mapper warnings