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Mike's update

Lab 4
2003-10-13
2003-10-13
  • Michael Chen

    Michael Chen - 2003-10-13

    I didn't plan to work until 4 am this morning, but I did it anyway, because the testers need some serious help. 

    I fixed some bugs in the monitor, now it's printing correctly from the pipeline.  However, there is still one bug that need to be fix.  When we run it during simulation, it didn't print nop during the break for the instructions before the break. 

    Brian, we seriously need you to work on the project tomorrow morning to get it done. 

    We need to debounce the release signal, which can be done the same way I did to the reset signal in toplevel.  I used a setResetRegister to generate the reset signal.  We need to write a simple testBench for the module though, it will take us 20 minutes.  It can be used to generate a syncronous signal.

    I think the problem with outputing ifInstruction straight from the instMem is it's not getting clock.  The address to instMem on reset is not getting clk in a register, so I won't expect to see it coming out to the led.  I suspect it might be in the ifIdReg, can someone run testAddress0 to test it. 

    Jason, are we meeting at 4 pm tomorrow in the lab.
    It seems everything is running.  We need someone to go over the proj spec to make sure we done everything, probably Brian. 

    I know everyone are stressed out and over work.  I think we can make it by 4 pm. 

     
    • Michael Chen

      Michael Chen - 2003-10-13

      I am coming in at 1 pm to fix some of the bugs, and make top level work hopefully!

       

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