This is from the datapath without forwarding, or hazardDetect. Also the clkDll has been removed to get this far.
Design Summary
--------------
Number of errors: 0
Number of warnings: 1
Logic Utilization:
Number of Slice Flip Flops: 1,604 out of 38,400 4%
Number of 4 input LUTs: 3,253 out of 38,400 8%
Logic Distribution:
Number of occupied Slices: 2,275 out of 19,200 11%
Number of Slices containing only related logic: 2,275 out of 2,275 100%
Number of Slices containing unrelated logic: 0 out of 2,275 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 3,268 out of 38,400 8%
Number used as logic: 3,253
Number used as a route-thru: 15
Number of bonded IOBs: 86 out of 512 16%
Number of Block RAMs: 32 out of 160 20%
Number of GCLKs: 2 out of 4 50%
Number of GCLKIOBs: 1 out of 4 25%
Total equivalent gate count for design: 561,086
Additional JTAG gate count for IOBs: 4,176
Peak Memory Usage: 136 MB
______________________________________________________________________________________
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Cpu.v's stat output should be 8 bits, its currently only 7 bits. I'll fix cpu.v so it quits complaining, but Brian you needa update the schematic.
Shifter.v doesn't work in synthesis. I don't think >>> is valid syntax outside of modelsim.
Mike, rethink implementation asap.
Shifter has been fixed.
This is from the datapath without forwarding, or hazardDetect. Also the clkDll has been removed to get this far.
Design Summary
--------------
Number of errors: 0
Number of warnings: 1
Logic Utilization:
Number of Slice Flip Flops: 1,604 out of 38,400 4%
Number of 4 input LUTs: 3,253 out of 38,400 8%
Logic Distribution:
Number of occupied Slices: 2,275 out of 19,200 11%
Number of Slices containing only related logic: 2,275 out of 2,275 100%
Number of Slices containing unrelated logic: 0 out of 2,275 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 3,268 out of 38,400 8%
Number used as logic: 3,253
Number used as a route-thru: 15
Number of bonded IOBs: 86 out of 512 16%
Number of Block RAMs: 32 out of 160 20%
Number of GCLKs: 2 out of 4 50%
Number of GCLKIOBs: 1 out of 4 25%
Total equivalent gate count for design: 561,086
Additional JTAG gate count for IOBs: 4,176
Peak Memory Usage: 136 MB
______________________________________________________________________________________
Brian, it appears that Jack said stuff in lab lecture which counters that which appears in the lab4 doc.
As of now, I will accept the 7 bit stat value, and the warnings should also disappear from synplify cause I have modified processor.v to pad stat.
We've changed back to 8 bits.
the eighth bit is the break signal from controller