- There does not seem to be any effort made to forward data to the mem stage of the pipeline, for the SW inst.
- Additionally, ex??? Wires where jumping across the regExMem boundary and controlling/writing to data memory.
- we adding a mux to forward data from the corresponding WB stage and a super special END stage which represents data values needed by SW after the WB stage. We are adding additional control signals and expanding registers as necessary.
- All of this is based on the rt reg used for SW.
jason / brandon
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dataForwarding should have a signal for memSrc, that selects between rt and memDataOut from wb stage, unless Brian didn't implement it base on the spec.
please update the spec on what you guys are doing, we need to be on the same sheet of music
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
- There does not seem to be any effort made to forward data to the mem stage of the pipeline, for the SW inst.
- Additionally, ex??? Wires where jumping across the regExMem boundary and controlling/writing to data memory.
- we adding a mux to forward data from the corresponding WB stage and a super special END stage which represents data values needed by SW after the WB stage. We are adding additional control signals and expanding registers as necessary.
- All of this is based on the rt reg used for SW.
jason / brandon
hopefully we are not smoking crack!
dataForwarding should have a signal for memSrc, that selects between rt and memDataOut from wb stage, unless Brian didn't implement it base on the spec.
please update the spec on what you guys are doing, we need to be on the same sheet of music