Brandon Ooi - 2003-10-12

WE HAVE LOCATED AND EXTERMINATED THE FOLLOWING BUGS

STALLS & DELAY SLOTS (3hr)
-stall was introducing a nop in the pipeline as expected. After that the instruction that was at pc plus eight was weaseling into the pipeline, and knocking out the instruction at pc plus four (the delay slot).
- We concluded that this instruction was a result of the latency on instruction memory reads.
- to solve the problem we brought an enable signal up from instMem and set it low on the cycle in which the stall is introduced in ID.

JAL (1hr)
- We found that the JAL instruction was not being executed correctly. Register 31 was getting the value PC + 4 rather than PC + 8.
- The reason for this was that the ALU B input was not being properly selected for the 32b4 input to be added to the (PC + 4.) This input was available but was not being properly selected.
- To solve the problem we corrected the design document control signal matrix for JAL such that the AluSrc signal was forced low, and corrected the corresponding code in the controller.

We are still working