Just in case any of you'll check this forum this morning, I plan on arriving in lab to start working on the next phase of cache testing/bug fixing at around 2pm, give or take.
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Brian, I changed the interfaces for Arbitrator.v and memController.v, please update the CPU accordingly.. And if you'd be kind enough to use ur windows account for adding to cvs, I think it'd be so much better, cause the code looks much cleaner without the extra new lines. :p
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Just in case any of you'll check this forum this morning, I plan on arriving in lab to start working on the next phase of cache testing/bug fixing at around 2pm, give or take.
Brian, I changed the interfaces for Arbitrator.v and memController.v, please update the CPU accordingly.. And if you'd be kind enough to use ur windows account for adding to cvs, I think it'd be so much better, cause the code looks much cleaner without the extra new lines. :p
I got here at 3:45 pm, no body was around.
I modified hazardDetect to only reset the register if we are not stalling else where, ie dataMemStall.
We can probably handle instMissStall the same way we handle dataPathStall.