In order to receive any benefit from victim cache, we must be able to read and write 8 words at once to and from the cache. It doesnt make sense to wait 16 cycles just to read and write when the data are right in front of you. Victim cache will need a valid signal from the cache when it's throwing out data, since it's 2 way, it only throws out data when it's full in both slots. Victim cache only interfaces with the cache, however it complicates the cachemiss a little bit, because it only misses if the data is not in the cache, writeBuffer and the victim cache. I think we still need to stall the pipeline, copy the entry that we are throwing away to the victim cache, and then copy the requested block from victim cache to the cache.
On this kind of stall, we don't need to serviced by the memController, so there are 2 kinds of miss signal from dataMem.
This brings to another problem, we need to keep the data in victim cache up to date, so we also need to write to the victim cache whenever we wrote to the writeBuffer if the data are in the victim cache. If we are doing a wide read and write, then we need to changed the way writeBuffer write back to the cache. The only way to make sure they are update to date is by writing back to the cache when we write back to the memory to both cache and victim cache.
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In order to receive any benefit from victim cache, we must be able to read and write 8 words at once to and from the cache. It doesnt make sense to wait 16 cycles just to read and write when the data are right in front of you. Victim cache will need a valid signal from the cache when it's throwing out data, since it's 2 way, it only throws out data when it's full in both slots. Victim cache only interfaces with the cache, however it complicates the cachemiss a little bit, because it only misses if the data is not in the cache, writeBuffer and the victim cache. I think we still need to stall the pipeline, copy the entry that we are throwing away to the victim cache, and then copy the requested block from victim cache to the cache.
On this kind of stall, we don't need to serviced by the memController, so there are 2 kinds of miss signal from dataMem.
This brings to another problem, we need to keep the data in victim cache up to date, so we also need to write to the victim cache whenever we wrote to the writeBuffer if the data are in the victim cache. If we are doing a wide read and write, then we need to changed the way writeBuffer write back to the cache. The only way to make sure they are update to date is by writing back to the cache when we write back to the memory to both cache and victim cache.