I spent the last 8 hours debugging the processor trying to figure out what's wrong. I started in instmem, but most of the problems with clobbering values can be resolved if dataHazarding DOESN'T flush the if register all the time when we have an instMiss.
All the problems I've encountered seemed to revolve around which parts of the pipeline are being flushed when we have cache misses. I really think we should rethink about what exactly a cache miss means to our pipeline, and how we can ensure that we dont' clobber data values.
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There are 4 types of stalls in our new pipeling, namely instMiss, dataMiss, bufferFull and our old friend dataPathStall. Here's what I think need to happen, on an instMiss stall, if there is no dataPathStall, we need to flush the ifIdReg, because if there is an addu $1, $1, $2, reg 1 will be incremented many times by $2 by the forwarding logic, and it might cause other problems like stall if we have lw $1, 0($1).
BufferFull, we might not need to stall immediately for a bufferFull, until we receive another sw in the execution stage, bufferFull should tell the arbiter to immediately clear out the buffer.
We don't need to flush the whole pipeline if there is a dataMiss stall, we just stall the whole pipeline.
In particular, we should let it sit there because we might need to forward the data to execution stage.
Right now, I don't see any changes to our dataPath stall.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
I spent the last 8 hours debugging the processor trying to figure out what's wrong. I started in instmem, but most of the problems with clobbering values can be resolved if dataHazarding DOESN'T flush the if register all the time when we have an instMiss.
All the problems I've encountered seemed to revolve around which parts of the pipeline are being flushed when we have cache misses. I really think we should rethink about what exactly a cache miss means to our pipeline, and how we can ensure that we dont' clobber data values.
There are 4 types of stalls in our new pipeling, namely instMiss, dataMiss, bufferFull and our old friend dataPathStall. Here's what I think need to happen, on an instMiss stall, if there is no dataPathStall, we need to flush the ifIdReg, because if there is an addu $1, $1, $2, reg 1 will be incremented many times by $2 by the forwarding logic, and it might cause other problems like stall if we have lw $1, 0($1).
BufferFull, we might not need to stall immediately for a bufferFull, until we receive another sw in the execution stage, bufferFull should tell the arbiter to immediately clear out the buffer.
We don't need to flush the whole pipeline if there is a dataMiss stall, we just stall the whole pipeline.
In particular, we should let it sit there because we might need to forward the data to execution stage.
Right now, I don't see any changes to our dataPath stall.