Synplify Warnings - Learn to code Biatches!

[Alan Tse]

@W: databoardram.v(58): No assignment to memoryLines_0_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_1_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_2_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_3_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_4_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_5_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_6_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_7_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_8_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_9_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_10_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_11_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_12_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_13_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_14_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_15_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_16_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_17_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_18_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_19_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_20_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_21_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_22_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_23_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_24_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_25_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_26_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_27_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_28_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_29_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_30_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(58): No assignment to memoryLines_31_ @W:"u:\lab5\databoardram.v":58:11:58:22
@W: databoardram.v(60): No assignment to tempcount @W:"u:\lab5\databoardram.v":60:4:60:13
@W: directcache.v(90): Port width mismatch for port we.  Formal has width 1, Actual 32 @W:"u:\lab5\directcache.v":90:58:90:65
@W: directcache.v(90): Port width mismatch for port do.  Formal has width 32, Actual 1 @W:"u:\lab5\directcache.v":90:67:90:72
@W: directcache.v(63): *Output dataOut has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(55): Input writeEnb is unused @W:"u:\lab5\directcache.v":55:6:55:14
@W: directcache.v(58): Input dataIn is unused @W:"u:\lab5\directcache.v":58:13:58:19
@W: writebuffer.v(50): No assignment to readState @W:"u:\lab5\writebuffer.v":50:4:50:13
@W: writebuffer.v(24): Input readEnb is unused @W:"u:\lab5\writebuffer.v":24:6:24:13
@W: cornerboardram.v(58): No assignment to memoryLines_0_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_1_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_2_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_3_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_4_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_5_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_6_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_7_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_8_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_9_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_10_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_11_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_12_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_13_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_14_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_15_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_16_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_17_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_18_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_19_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_20_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_21_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_22_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_23_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_24_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_25_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_26_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_27_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_28_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_29_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_30_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(58): No assignment to memoryLines_31_ @W:"u:\lab5\cornerboardram.v":58:11:58:22
@W: cornerboardram.v(60): No assignment to tempcount @W:"u:\lab5\cornerboardram.v":60:4:60:13
@W: instmem.v(89): Undriven input ioIn, tying to 0 @W:"u:\lab5\instmem.v":89:5:89:9
@W: instmem.v(91): Undriven input ioSelect, tying to 0 @W:"u:\lab5\instmem.v":91:5:91:13
@W: instmem.v(92): Undriven input we, tying to 0 @W:"u:\lab5\instmem.v":92:5:92:7
@W: instmem.v(26): No assignment to regEn @W:"u:\lab5\instmem.v":26:11:26:16
@W: instmem.v(32): No assignment to doutReg @W:"u:\lab5\instmem.v":32:17:32:24
@W: register.v(11): Ignoring initial statement @W:"u:\lab5\register.v":11:1:11:8
@W: register.v(11): Ignoring initial statement @W:"u:\lab5\register.v":11:1:11:8
@W: buffer.v(70): Incomplete sensitivity list - assuming completeness @W:"u:\lab5\buffer.v":70:12:70:42
@W: buffer.v(86): Referenced variable writeToggle2 is not in sensitivity list @W:"u:\lab5\buffer.v":86:25:86:37
@W: buffer.v(80): Referenced variable readToggle2 is not in sensitivity list @W:"u:\lab5\buffer.v":80:24:80:35
@W: buffer.v(72): Latch generated from always block for signal writePtr[9:0], probably caused by a missing assignment in an if or case stmt @W:"u:\lab5\buffer.v":72:1:72:3
@W: buffer.v(72): Latch generated from always block for signal readPtr[9:0], probably caused by a missing assignment in an if or case stmt @W:"u:\lab5\buffer.v":72:1:72:3
@W: buffer.v(11): Input in is unused @W:"u:\lab5\buffer.v":11:22:11:24
@W: buffer.v(12): Input we is unused @W:"u:\lab5\buffer.v":12:16:12:18
@W: buffer.v(13): Input rst is unused @W:"u:\lab5\buffer.v":13:8:13:11
@W: buffer.v(14): Input clk1 is unused @W:"u:\lab5\buffer.v":14:8:14:12
@W: buffer.v(16): Input re is unused @W:"u:\lab5\buffer.v":16:8:16:10
@W: register.v(11): Ignoring initial statement @W:"u:\lab5\register.v":11:1:11:8
@W: pulsesync.v(17): *Input rst to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible @W:"u:\lab5\pulsesync.v":17:12:17:14
@W: memcontroller.v(402): Register bit CS is always 0, optimizing ... @W:"u:\lab5\memcontroller.v":402:3:402:9
@W: memcontroller.v(402): Register bit DQM[1] is always 0, optimizing ... @W:"u:\lab5\memcontroller.v":402:3:402:9
@W: monitor.v(116): Ignoring initial statement @W:"u:\lab5\monitor.v":116:3:116:10
@W: monitor.v(112): No assignment to file @W:"u:\lab5\monitor.v":112:12:112:16
@W: monitor.v(18): Input clk is unused @W:"u:\lab5\monitor.v":18:9:18:12
@W: monitor.v(19): Input address is unused @W:"u:\lab5\monitor.v":19:16:19:23
@W: monitor.v(20): Input instruction is unused @W:"u:\lab5\monitor.v":20:2:20:13
@W: monitor.v(21): Input memOutput is unused @W:"u:\lab5\monitor.v":21:2:21:11
@W: monitor.v(22): Input regOutA is unused @W:"u:\lab5\monitor.v":22:2:22:9
@W: monitor.v(23): Input regOutB is unused @W:"u:\lab5\monitor.v":23:2:23:9
@W: monitor.v(25): Input aluSrc0 is unused @W:"u:\lab5\monitor.v":25:3:25:10
@W: monitor.v(26): Input aluSrc1 is unused @W:"u:\lab5\monitor.v":26:2:26:9
@W: monitor.v(27): Input exMemDataIn is unused @W:"u:\lab5\monitor.v":27:2:27:13
@W: monitor.v(24): Input aluOut is unused @W:"u:\lab5\monitor.v":24:2:24:8
@W: monitor.v(28): Input nextPc is unused @W:"u:\lab5\monitor.v":28:2:28:8
@W: monitor.v(31): Input stall is unused @W:"u:\lab5\monitor.v":31:10:31:15
@W: monitor.v(32): Input dump is unused @W:"u:\lab5\monitor.v":32:2:32:6
@W: monitor.v(29): Input debugOut is unused @W:"u:\lab5\monitor.v":29:2:29:10
@W: regfile.v(32): Register 'file_0_' is only assigned 0 or its old value; the register will be removed @W:"u:\lab5\regfile.v":32:3:32:9
@W: regfile.v(13): Input dump is unused @W:"u:\lab5\regfile.v":13:36:13:40
@W: cpu.v(237): Undriven input dump, tying to 0 @W:"u:\lab5\cpu.v":237:48:237:52
@W: toplevel.v(406): Undriven input dump, tying to 0 @W:"u:\lab5\toplevel.v":406:5:406:9
@W: toplevel.v(405): Port width mismatch for port debugOut.  Formal has width 32, Actual 8 @W:"u:\lab5\toplevel.v":405:14:405:22
@W: toplevel.v(145): *Output RJ45_TRC has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":145:17:145:25
@W: toplevel.v(146): *Output RJ45_BRC has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":146:17:146:25
@W: toplevel.v(147): *Output RJ45_TLC has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":147:17:147:25
@W: toplevel.v(148): *Output RJ45_BLC has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":148:17:148:25
@W: toplevel.v(154): *Output PHY_ADD_ has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":154:17:154:25
@W: toplevel.v(158): *Output PHY_MDC has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":158:12:158:19
@W: toplevel.v(159): *Output PHY_MDDIS has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":159:12:159:21
@W: toplevel.v(160): *Output PHY_PWRDN has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":160:12:160:21
@W: toplevel.v(161): *Output PHY_RESET has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":161:12:161:21
@W: toplevel.v(162): *Output PHY_FDE has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":162:12:162:19
@W: toplevel.v(163): *Output PHY_AUTOENA has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":163:12:163:23
@W: toplevel.v(164): *Output PHY_BYPSCR has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":164:12:164:22
@W: toplevel.v(165): *Output PHY_CFG_ has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":165:17:165:25
@W: toplevel.v(177): *Output PHY_TX_ER_ has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":177:17:177:27
@W: toplevel.v(179): *Output PHY_TX_EN_ has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":179:17:179:27
@W: toplevel.v(180): *Output PHY_TXD0_ has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":180:17:180:26
@W: toplevel.v(181): *Output PHY_TXD1_ has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":181:17:181:26
@W: toplevel.v(182): *Output PHY_TXD2_ has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":182:17:182:26
@W: toplevel.v(183): *Output PHY_TXD3_ has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":183:17:183:26
@W: toplevel.v(186): *Output PHY_TRSTE_ has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":186:17:186:27
@W: toplevel.v(191): *Output AP_SDATA_IN has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":191:12:191:23
@W: toplevel.v(192): *Output AP_SYNC has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":192:12:192:19
@W: toplevel.v(193): *Output AP_RESET_B has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":193:12:193:22
@W: toplevel.v(194): *Output AP_PC_BEEP has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":194:12:194:22
@W: toplevel.v(196): *Output AA_MUTE has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":196:12:196:19
@W: toplevel.v(202): *Output RAM_DQMH has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":202:12:202:20
@W: toplevel.v(217): *Output ACE_MPIRQ has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":217:12:217:21
@W: toplevel.v(218): *Output ACE_MPCE_B has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":218:12:218:22
@W: toplevel.v(219): *Output ACE_MPWE_B has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":219:12:219:22
@W: toplevel.v(220): *Output ACE_MPOE_B has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":220:12:220:22
@W: toplevel.v(221): *Output ACE_MPA has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":221:17:221:24
@W: toplevel.v(225): *Output VE_P has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":225:17:225:21
@W: toplevel.v(227): *Output VE_SDA has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":227:12:227:18
@W: toplevel.v(229): *Output VE_RESET_B has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":229:12:229:22
@W: toplevel.v(233): *Output VE_SCRESET has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":233:12:233:22
@W: toplevel.v(235): *Output VE_CLKIN_ has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":235:9:235:18
@W: toplevel.v(244): *Output VD_RESET_B has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":244:12:244:22
@W: toplevel.v(302): *Output SEG_PT_ has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":302:14:302:20
@W: toplevel.v(261): *Output PINOUT_TOP_CLOSE has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(262): *Output PINOUT_TOP_FAR has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(263): *Output PINOUT_LEFT_CLOSE has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(264): *Output PINOUT_LEFT_FAR has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(265): *Output PINOUT_BOTTOM_CLOSE has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(266): *Output PINOUT_BOTTOM_FAR has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(267): *Output PINOUT_RIGHT_CLOSE has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(268): *Output PINOUT_RIGHT_FAR has undriven bits - a simulation mismatch is possible  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(151): Input PHY_LEDCLK is unused @W:"u:\lab5\toplevel.v":151:11:151:21
@W: toplevel.v(152): Input PHY_LEDDAT is unused @W:"u:\lab5\toplevel.v":152:11:152:21
@W: toplevel.v(153): Input PHY_LEDENA is unused @W:"u:\lab5\toplevel.v":153:11:153:21
@W: toplevel.v(156): Input PHY_MDIO is unused @W:"u:\lab5\toplevel.v":156:11:156:19
@W: toplevel.v(157): Input PHY_MDINT is unused @W:"u:\lab5\toplevel.v":157:11:157:20
@W: toplevel.v(166): Input PHY_LED0_ is unused @W:"u:\lab5\toplevel.v":166:17:166:26
@W: toplevel.v(167): Input PHY_LED1_ is unused @W:"u:\lab5\toplevel.v":167:17:167:26
@W: toplevel.v(168): Input PHY_LED2_ is unused @W:"u:\lab5\toplevel.v":168:17:168:26
@W: toplevel.v(169): Input PHY_LED3_ is unused @W:"u:\lab5\toplevel.v":169:17:169:26
@W: toplevel.v(170): Input PHY_RXD0_ is unused @W:"u:\lab5\toplevel.v":170:17:170:26
@W: toplevel.v(171): Input PHY_RXD1_ is unused @W:"u:\lab5\toplevel.v":171:17:171:26
@W: toplevel.v(172): Input PHY_RXD2_ is unused @W:"u:\lab5\toplevel.v":172:17:172:26
@W: toplevel.v(173): Input PHY_RXD3_ is unused @W:"u:\lab5\toplevel.v":173:17:173:26
@W: toplevel.v(174): Input PHY_RX_DV_ is unused @W:"u:\lab5\toplevel.v":174:17:174:27
@W: toplevel.v(175): Input PHY_RX_CLK_ is unused @W:"u:\lab5\toplevel.v":175:17:175:87
@W: toplevel.v(176): Input PHY_RX_ER_ is unused @W:"u:\lab5\toplevel.v":176:17:176:27
@W: toplevel.v(178): Input PHY_TX_CLK_ is unused @W:"u:\lab5\toplevel.v":178:17:178:28
@W: toplevel.v(184): Input PHY_COL_ is unused @W:"u:\lab5\toplevel.v":184:17:184:25
@W: toplevel.v(185): Input PHY_CRS_ is unused @W:"u:\lab5\toplevel.v":185:17:185:25
@W: toplevel.v(189): Input AP_SDATA_OUT is unused @W:"u:\lab5\toplevel.v":189:11:189:23
@W: toplevel.v(190): Input AP_BIT_CLOCK is unused @W:"u:\lab5\toplevel.v":190:11:190:23
@W: toplevel.v(216): Input ACE_MPBRDY is unused @W:"u:\lab5\toplevel.v":216:11:216:21
@W: toplevel.v(222): Inout ACE_MPD is unused @W:"u:\lab5\toplevel.v":222:17:222:24
@W: toplevel.v(226): Input VE_SCLK is unused @W:"u:\lab5\toplevel.v":226:11:226:18
@W: toplevel.v(228): Input VE_PAL_NTSC is unused @W:"u:\lab5\toplevel.v":228:11:228:22
@W: toplevel.v(230): Input VE_HSYNC_B is unused @W:"u:\lab5\toplevel.v":230:11:230:21
@W: toplevel.v(231): Input VE_VSYNC_B is unused @W:"u:\lab5\toplevel.v":231:11:231:21
@W: toplevel.v(232): Input VE_BLANK_B is unused @W:"u:\lab5\toplevel.v":232:11:232:21
@W: toplevel.v(238): Input VD_CLOCK is unused @W:"u:\lab5\toplevel.v":238:11:238:19
@W: toplevel.v(240): Input VD_CHAN1_DATA is unused @W:"u:\lab5\toplevel.v":240:17:240:30
@W: toplevel.v(241): Input VD_CHAN1_I2C_CLOCK is unused @W:"u:\lab5\toplevel.v":241:11:241:29

@W: toplevel.v(242): Input VD_CHAN1_I2C_DATA is unused @W:"u:\lab5\toplevel.v":242:11:242:28
@W: toplevel.v(243): Input VD_CHAN1_ISO is unused @W:"u:\lab5\toplevel.v":243:11:243:23
@W: toplevel.v(227): tristate driver VE_SDA on net VE_SDA has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":227:12:227:18
@W: toplevel.v(233): tristate driver VE_SCRESET on net VE_SCRESET has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":233:12:233:22
@W: toplevel.v(229): tristate driver VE_RESET_B on net VE_RESET_B has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":229:12:229:22
@W: toplevel.v(225): tristate driver VE_P_10 on net VE_P_10 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":225:17:225:21
@W: toplevel.v(225): tristate driver VE_P_9 on net VE_P_9 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":225:17:225:21
@W: toplevel.v(225): tristate driver VE_P_8 on net VE_P_8 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":225:17:225:21
@W: toplevel.v(225): tristate driver VE_P_7 on net VE_P_7 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":225:17:225:21
@W: toplevel.v(225): tristate driver VE_P_6 on net VE_P_6 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":225:17:225:21
@W: toplevel.v(225): tristate driver VE_P_5 on net VE_P_5 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":225:17:225:21
@W: toplevel.v(225): tristate driver VE_P_4 on net VE_P_4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":225:17:225:21
@W: toplevel.v(225): tristate driver VE_P_3 on net VE_P_3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":225:17:225:21
@W: toplevel.v(225): tristate driver VE_P_2 on net VE_P_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":225:17:225:21
@W: toplevel.v(225): tristate driver VE_P_1 on net VE_P_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":225:17:225:21
@W: toplevel.v(235): tristate driver VE_CLKIN_ on net VE_CLKIN_ has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":235:9:235:18
@W: toplevel.v(244): tristate driver VD_RESET_B on net VD_RESET_B has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":244:12:244:22
@W: toplevel.v(302): tristate driver SEG_PT__8 on net SEG_PT__8 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":302:14:302:20
@W: toplevel.v(302): tristate driver SEG_PT__7 on net SEG_PT__7 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":302:14:302:20
@W: toplevel.v(302): tristate driver SEG_PT__6 on net SEG_PT__6 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":302:14:302:20
@W: toplevel.v(302): tristate driver SEG_PT__5 on net SEG_PT__5 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":302:14:302:20
@W: toplevel.v(302): tristate driver SEG_PT__4 on net SEG_PT__4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":302:14:302:20
@W: toplevel.v(302): tristate driver SEG_PT__3 on net SEG_PT__3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":302:14:302:20
@W: toplevel.v(302): tristate driver SEG_PT__2 on net SEG_PT__2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":302:14:302:20
@W: toplevel.v(302): tristate driver SEG_PT__1 on net SEG_PT__1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":302:14:302:20
@W: toplevel.v(145): tristate driver RJ45_TRC_2 on net RJ45_TRC_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":145:17:145:25
@W: toplevel.v(145): tristate driver RJ45_TRC_1 on net RJ45_TRC_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":145:17:145:25
@W: toplevel.v(147): tristate driver RJ45_TLC_2 on net RJ45_TLC_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":147:17:147:25
@W: toplevel.v(147): tristate driver RJ45_TLC_1 on net RJ45_TLC_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":147:17:147:25
@W: toplevel.v(146): tristate driver RJ45_BRC_2 on net RJ45_BRC_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":146:17:146:25
@W: toplevel.v(146): tristate driver RJ45_BRC_1 on net RJ45_BRC_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":146:17:146:25
@W: toplevel.v(148): tristate driver RJ45_BLC_2 on net RJ45_BLC_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":148:17:148:25
@W: toplevel.v(148): tristate driver RJ45_BLC_1 on net RJ45_BLC_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":148:17:148:25
@W: toplevel.v(202): tristate driver RAM_DQMH on net RAM_DQMH has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":202:12:202:20
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_20 on net PINOUT_TOP_FAR_20 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_19 on net PINOUT_TOP_FAR_19 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_18 on net PINOUT_TOP_FAR_18 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_17 on net PINOUT_TOP_FAR_17 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_16 on net PINOUT_TOP_FAR_16 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_15 on net PINOUT_TOP_FAR_15 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_14 on net PINOUT_TOP_FAR_14 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_13 on net PINOUT_TOP_FAR_13 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_12 on net PINOUT_TOP_FAR_12 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_11 on net PINOUT_TOP_FAR_11 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_10 on net PINOUT_TOP_FAR_10 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_9 on net PINOUT_TOP_FAR_9 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_8 on net PINOUT_TOP_FAR_8 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_7 on net PINOUT_TOP_FAR_7 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_6 on net PINOUT_TOP_FAR_6 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_5 on net PINOUT_TOP_FAR_5 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_4 on net PINOUT_TOP_FAR_4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_3 on net PINOUT_TOP_FAR_3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_2 on net PINOUT_TOP_FAR_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(262): tristate driver PINOUT_TOP_FAR_1 on net PINOUT_TOP_FAR_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":262:18:262:32
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_20 on net PINOUT_TOP_CLOSE_20 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_19 on net PINOUT_TOP_CLOSE_19 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_18 on net PINOUT_TOP_CLOSE_18 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_17 on net PINOUT_TOP_CLOSE_17 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_16 on net PINOUT_TOP_CLOSE_16 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_15 on net PINOUT_TOP_CLOSE_15 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_14 on net PINOUT_TOP_CLOSE_14 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_13 on net PINOUT_TOP_CLOSE_13 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_12 on net PINOUT_TOP_CLOSE_12 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_11 on net PINOUT_TOP_CLOSE_11 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_10 on net PINOUT_TOP_CLOSE_10 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_9 on net PINOUT_TOP_CLOSE_9 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_8 on net PINOUT_TOP_CLOSE_8 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_7 on net PINOUT_TOP_CLOSE_7 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_6 on net PINOUT_TOP_CLOSE_6 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_5 on net PINOUT_TOP_CLOSE_5 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_4 on net PINOUT_TOP_CLOSE_4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_3 on net PINOUT_TOP_CLOSE_3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_2 on net PINOUT_TOP_CLOSE_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(261): tristate driver PINOUT_TOP_CLOSE_1 on net PINOUT_TOP_CLOSE_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":261:18:261:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_20 on net PINOUT_RIGHT_FAR_20 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_19 on net PINOUT_RIGHT_FAR_19 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_18 on net PINOUT_RIGHT_FAR_18 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_17 on net PINOUT_RIGHT_FAR_17 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_16 on net PINOUT_RIGHT_FAR_16 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_15 on net PINOUT_RIGHT_FAR_15 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_14 on net PINOUT_RIGHT_FAR_14 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_13 on net PINOUT_RIGHT_FAR_13 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_12 on net PINOUT_RIGHT_FAR_12 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_11 on net PINOUT_RIGHT_FAR_11 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_10 on net PINOUT_RIGHT_FAR_10 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_9 on net PINOUT_RIGHT_FAR_9 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_8 on net PINOUT_RIGHT_FAR_8 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_7 on net PINOUT_RIGHT_FAR_7 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_6 on net PINOUT_RIGHT_FAR_6 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_5 on net PINOUT_RIGHT_FAR_5 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_4 on net PINOUT_RIGHT_FAR_4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_3 on net PINOUT_RIGHT_FAR_3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_2 on net PINOUT_RIGHT_FAR_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(268): tristate driver PINOUT_RIGHT_FAR_1 on net PINOUT_RIGHT_FAR_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":268:18:268:34
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_20 on net PINOUT_RIGHT_CLOSE_20 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_19 on net PINOUT_RIGHT_CLOSE_19 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_18 on net PINOUT_RIGHT_CLOSE_18 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_17 on net PINOUT_RIGHT_CLOSE_17 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_16 on net PINOUT_RIGHT_CLOSE_16 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_15 on net PINOUT_RIGHT_CLOSE_15 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_14 on net PINOUT_RIGHT_CLOSE_14 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_13 on net PINOUT_RIGHT_CLOSE_13 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_12 on net PINOUT_RIGHT_CLOSE_12 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_11 on net PINOUT_RIGHT_CLOSE_11 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_10 on net PINOUT_RIGHT_CLOSE_10 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_9 on net PINOUT_RIGHT_CLOSE_9 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_8 on net PINOUT_RIGHT_CLOSE_8 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_7 on net PINOUT_RIGHT_CLOSE_7 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_6 on net PINOUT_RIGHT_CLOSE_6 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_5 on net PINOUT_RIGHT_CLOSE_5 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_4 on net PINOUT_RIGHT_CLOSE_4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_3 on net PINOUT_RIGHT_CLOSE_3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_2 on net PINOUT_RIGHT_CLOSE_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(267): tristate driver PINOUT_RIGHT_CLOSE_1 on net PINOUT_RIGHT_CLOSE_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":267:18:267:36
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_20 on net PINOUT_LEFT_FAR_20 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_19 on net PINOUT_LEFT_FAR_19 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_18 on net PINOUT_LEFT_FAR_18 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_17 on net PINOUT_LEFT_FAR_17 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_16 on net PINOUT_LEFT_FAR_16 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_15 on net PINOUT_LEFT_FAR_15 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_14 on net PINOUT_LEFT_FAR_14 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_13 on net PINOUT_LEFT_FAR_13 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_12 on net PINOUT_LEFT_FAR_12 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_11 on net PINOUT_LEFT_FAR_11 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33

@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_10 on net PINOUT_LEFT_FAR_10 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_9 on net PINOUT_LEFT_FAR_9 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_8 on net PINOUT_LEFT_FAR_8 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_7 on net PINOUT_LEFT_FAR_7 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_6 on net PINOUT_LEFT_FAR_6 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_5 on net PINOUT_LEFT_FAR_5 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_4 on net PINOUT_LEFT_FAR_4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_3 on net PINOUT_LEFT_FAR_3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_2 on net PINOUT_LEFT_FAR_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(264): tristate driver PINOUT_LEFT_FAR_1 on net PINOUT_LEFT_FAR_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":264:18:264:33
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_20 on net PINOUT_LEFT_CLOSE_20 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_19 on net PINOUT_LEFT_CLOSE_19 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_18 on net PINOUT_LEFT_CLOSE_18 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_17 on net PINOUT_LEFT_CLOSE_17 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_16 on net PINOUT_LEFT_CLOSE_16 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_15 on net PINOUT_LEFT_CLOSE_15 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_14 on net PINOUT_LEFT_CLOSE_14 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_13 on net PINOUT_LEFT_CLOSE_13 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_12 on net PINOUT_LEFT_CLOSE_12 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_11 on net PINOUT_LEFT_CLOSE_11 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_10 on net PINOUT_LEFT_CLOSE_10 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_9 on net PINOUT_LEFT_CLOSE_9 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_8 on net PINOUT_LEFT_CLOSE_8 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_7 on net PINOUT_LEFT_CLOSE_7 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_6 on net PINOUT_LEFT_CLOSE_6 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_5 on net PINOUT_LEFT_CLOSE_5 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_4 on net PINOUT_LEFT_CLOSE_4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_3 on net PINOUT_LEFT_CLOSE_3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_2 on net PINOUT_LEFT_CLOSE_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(263): tristate driver PINOUT_LEFT_CLOSE_1 on net PINOUT_LEFT_CLOSE_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":263:18:263:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_20 on net PINOUT_BOTTOM_FAR_20 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_19 on net PINOUT_BOTTOM_FAR_19 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_18 on net PINOUT_BOTTOM_FAR_18 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_17 on net PINOUT_BOTTOM_FAR_17 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_16 on net PINOUT_BOTTOM_FAR_16 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_15 on net PINOUT_BOTTOM_FAR_15 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_14 on net PINOUT_BOTTOM_FAR_14 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_13 on net PINOUT_BOTTOM_FAR_13 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_12 on net PINOUT_BOTTOM_FAR_12 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_11 on net PINOUT_BOTTOM_FAR_11 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_10 on net PINOUT_BOTTOM_FAR_10 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_9 on net PINOUT_BOTTOM_FAR_9 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_8 on net PINOUT_BOTTOM_FAR_8 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_7 on net PINOUT_BOTTOM_FAR_7 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_6 on net PINOUT_BOTTOM_FAR_6 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_5 on net PINOUT_BOTTOM_FAR_5 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_4 on net PINOUT_BOTTOM_FAR_4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_3 on net PINOUT_BOTTOM_FAR_3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_2 on net PINOUT_BOTTOM_FAR_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(266): tristate driver PINOUT_BOTTOM_FAR_1 on net PINOUT_BOTTOM_FAR_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":266:18:266:35
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_20 on net PINOUT_BOTTOM_CLOSE_20 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_19 on net PINOUT_BOTTOM_CLOSE_19 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_18 on net PINOUT_BOTTOM_CLOSE_18 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_17 on net PINOUT_BOTTOM_CLOSE_17 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_16 on net PINOUT_BOTTOM_CLOSE_16 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_15 on net PINOUT_BOTTOM_CLOSE_15 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_14 on net PINOUT_BOTTOM_CLOSE_14 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_13 on net PINOUT_BOTTOM_CLOSE_13 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_12 on net PINOUT_BOTTOM_CLOSE_12 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_11 on net PINOUT_BOTTOM_CLOSE_11 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_10 on net PINOUT_BOTTOM_CLOSE_10 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_9 on net PINOUT_BOTTOM_CLOSE_9 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_8 on net PINOUT_BOTTOM_CLOSE_8 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_7 on net PINOUT_BOTTOM_CLOSE_7 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_6 on net PINOUT_BOTTOM_CLOSE_6 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_5 on net PINOUT_BOTTOM_CLOSE_5 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_4 on net PINOUT_BOTTOM_CLOSE_4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_3 on net PINOUT_BOTTOM_CLOSE_3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_2 on net PINOUT_BOTTOM_CLOSE_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(265): tristate driver PINOUT_BOTTOM_CLOSE_1 on net PINOUT_BOTTOM_CLOSE_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":265:18:265:37
@W: toplevel.v(177): tristate driver PHY_TX_ER__4 on net PHY_TX_ER__4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":177:17:177:27
@W: toplevel.v(177): tristate driver PHY_TX_ER__3 on net PHY_TX_ER__3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":177:17:177:27
@W: toplevel.v(177): tristate driver PHY_TX_ER__2 on net PHY_TX_ER__2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":177:17:177:27
@W: toplevel.v(177): tristate driver PHY_TX_ER__1 on net PHY_TX_ER__1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":177:17:177:27
@W: toplevel.v(179): tristate driver PHY_TX_EN__4 on net PHY_TX_EN__4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":179:17:179:27
@W: toplevel.v(179): tristate driver PHY_TX_EN__3 on net PHY_TX_EN__3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":179:17:179:27
@W: toplevel.v(179): tristate driver PHY_TX_EN__2 on net PHY_TX_EN__2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":179:17:179:27
@W: toplevel.v(179): tristate driver PHY_TX_EN__1 on net PHY_TX_EN__1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":179:17:179:27
@W: toplevel.v(183): tristate driver PHY_TXD3__4 on net PHY_TXD3__4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":183:17:183:26
@W: toplevel.v(183): tristate driver PHY_TXD3__3 on net PHY_TXD3__3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":183:17:183:26
@W: toplevel.v(183): tristate driver PHY_TXD3__2 on net PHY_TXD3__2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":183:17:183:26
@W: toplevel.v(183): tristate driver PHY_TXD3__1 on net PHY_TXD3__1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":183:17:183:26
@W: toplevel.v(182): tristate driver PHY_TXD2__4 on net PHY_TXD2__4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":182:17:182:26
@W: toplevel.v(182): tristate driver PHY_TXD2__3 on net PHY_TXD2__3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":182:17:182:26
@W: toplevel.v(182): tristate driver PHY_TXD2__2 on net PHY_TXD2__2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":182:17:182:26
@W: toplevel.v(182): tristate driver PHY_TXD2__1 on net PHY_TXD2__1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":182:17:182:26
@W: toplevel.v(181): tristate driver PHY_TXD1__4 on net PHY_TXD1__4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":181:17:181:26
@W: toplevel.v(181): tristate driver PHY_TXD1__3 on net PHY_TXD1__3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":181:17:181:26
@W: toplevel.v(181): tristate driver PHY_TXD1__2 on net PHY_TXD1__2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":181:17:181:26
@W: toplevel.v(181): tristate driver PHY_TXD1__1 on net PHY_TXD1__1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":181:17:181:26
@W: toplevel.v(180): tristate driver PHY_TXD0__4 on net PHY_TXD0__4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":180:17:180:26
@W: toplevel.v(180): tristate driver PHY_TXD0__3 on net PHY_TXD0__3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":180:17:180:26
@W: toplevel.v(180): tristate driver PHY_TXD0__2 on net PHY_TXD0__2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":180:17:180:26
@W: toplevel.v(180): tristate driver PHY_TXD0__1 on net PHY_TXD0__1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":180:17:180:26
@W: toplevel.v(186): tristate driver PHY_TRSTE__4 on net PHY_TRSTE__4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":186:17:186:27
@W: toplevel.v(186): tristate driver PHY_TRSTE__3 on net PHY_TRSTE__3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":186:17:186:27
@W: toplevel.v(186): tristate driver PHY_TRSTE__2 on net PHY_TRSTE__2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":186:17:186:27
@W: toplevel.v(186): tristate driver PHY_TRSTE__1 on net PHY_TRSTE__1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":186:17:186:27
@W: toplevel.v(161): tristate driver PHY_RESET on net PHY_RESET has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":161:12:161:21
@W: toplevel.v(160): tristate driver PHY_PWRDN on net PHY_PWRDN has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":160:12:160:21
@W: toplevel.v(159): tristate driver PHY_MDDIS on net PHY_MDDIS has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":159:12:159:21
@W: toplevel.v(158): tristate driver PHY_MDC on net PHY_MDC has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":158:12:158:19
@W: toplevel.v(162): tristate driver PHY_FDE on net PHY_FDE has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":162:12:162:19
@W: toplevel.v(165): tristate driver PHY_CFG__3 on net PHY_CFG__3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":165:17:165:25
@W: toplevel.v(165): tristate driver PHY_CFG__2 on net PHY_CFG__2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":165:17:165:25
@W: toplevel.v(165): tristate driver PHY_CFG__1 on net PHY_CFG__1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":165:17:165:25
@W: toplevel.v(164): tristate driver PHY_BYPSCR on net PHY_BYPSCR has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":164:12:164:22
@W: toplevel.v(163): tristate driver PHY_AUTOENA on net PHY_AUTOENA has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":163:12:163:23
@W: toplevel.v(154): tristate driver PHY_ADD__3 on net PHY_ADD__3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":154:17:154:25
@W: toplevel.v(154): tristate driver PHY_ADD__2 on net PHY_ADD__2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":154:17:154:25
@W: toplevel.v(154): tristate driver PHY_ADD__1 on net PHY_ADD__1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":154:17:154:25
@W: toplevel.v(192): tristate driver AP_SYNC on net AP_SYNC has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":192:12:192:19
@W: toplevel.v(191): tristate driver AP_SDATA_IN on net AP_SDATA_IN has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":191:12:191:23
@W: toplevel.v(193): tristate driver AP_RESET_B on net AP_RESET_B has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":193:12:193:22
@W: toplevel.v(194): tristate driver AP_PC_BEEP on net AP_PC_BEEP has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":194:12:194:22
@W: toplevel.v(219): tristate driver ACE_MPWE_B on net ACE_MPWE_B has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":219:12:219:22
@W: toplevel.v(220): tristate driver ACE_MPOE_B on net ACE_MPOE_B has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":220:12:220:22
@W: toplevel.v(217): tristate driver ACE_MPIRQ on net ACE_MPIRQ has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":217:12:217:21
@W: toplevel.v(218): tristate driver ACE_MPCE_B on net ACE_MPCE_B has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":218:12:218:22
@W: toplevel.v(221): tristate driver ACE_MPA_7 on net ACE_MPA_7 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":221:17:221:24
@W: toplevel.v(221): tristate driver ACE_MPA_6 on net ACE_MPA_6 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":221:17:221:24
@W: toplevel.v(221): tristate driver ACE_MPA_5 on net ACE_MPA_5 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":221:17:221:24
@W: toplevel.v(221): tristate driver ACE_MPA_4 on net ACE_MPA_4 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":221:17:221:24

@W: toplevel.v(221): tristate driver ACE_MPA_3 on net ACE_MPA_3 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":221:17:221:24
@W: toplevel.v(221): tristate driver ACE_MPA_2 on net ACE_MPA_2 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":221:17:221:24
@W: toplevel.v(221): tristate driver ACE_MPA_1 on net ACE_MPA_1 has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":221:17:221:24
@W: toplevel.v(196): tristate driver AA_MUTE on net AA_MUTE has its enable tied to GND (module TopLevel)  @W:"u:\lab5\toplevel.v":196:12:196:19
@W: tristate driver cacheDout_t[31] on net cacheDout[31] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[30] on net cacheDout[30] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[29] on net cacheDout[29] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[28] on net cacheDout[28] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[27] on net cacheDout[27] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[26] on net cacheDout[26] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[25] on net cacheDout[25] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[24] on net cacheDout[24] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[23] on net cacheDout[23] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[22] on net cacheDout[22] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[21] on net cacheDout[21] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[20] on net cacheDout[20] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[19] on net cacheDout[19] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[18] on net cacheDout[18] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[17] on net cacheDout[17] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[16] on net cacheDout[16] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[15] on net cacheDout[15] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[14] on net cacheDout[14] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[13] on net cacheDout[13] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[12] on net cacheDout[12] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[11] on net cacheDout[11] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[10] on net cacheDout[10] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[9] on net cacheDout[9] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[8] on net cacheDout[8] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[7] on net cacheDout[7] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[6] on net cacheDout[6] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[5] on net cacheDout[5] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[4] on net cacheDout[4] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[3] on net cacheDout[3] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[2] on net cacheDout[2] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[1] on net cacheDout[1] has its enable tied to GND (module instMem)
@W: tristate driver cacheDout_t[0] on net cacheDout[0] has its enable tied to GND (module instMem)
@W: tristate driver cacheDataOut_t[31] on net cacheDataOut[31] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[30] on net cacheDataOut[30] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[29] on net cacheDataOut[29] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[28] on net cacheDataOut[28] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[27] on net cacheDataOut[27] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[26] on net cacheDataOut[26] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[25] on net cacheDataOut[25] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[24] on net cacheDataOut[24] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[23] on net cacheDataOut[23] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[22] on net cacheDataOut[22] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[21] on net cacheDataOut[21] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[20] on net cacheDataOut[20] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[19] on net cacheDataOut[19] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[18] on net cacheDataOut[18] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[17] on net cacheDataOut[17] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[16] on net cacheDataOut[16] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[15] on net cacheDataOut[15] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[14] on net cacheDataOut[14] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[13] on net cacheDataOut[13] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[12] on net cacheDataOut[12] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[11] on net cacheDataOut[11] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[10] on net cacheDataOut[10] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[9] on net cacheDataOut[9] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[8] on net cacheDataOut[8] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[7] on net cacheDataOut[7] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[6] on net cacheDataOut[6] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[5] on net cacheDataOut[5] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[4] on net cacheDataOut[4] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[3] on net cacheDataOut[3] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[2] on net cacheDataOut[2] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[1] on net cacheDataOut[1] has its enable tied to GND (module datamem)
@W: tristate driver cacheDataOut_t[0] on net cacheDataOut[0] has its enable tied to GND (module datamem)
@W: directcache.v(63): tristate driver dataOut_32 on net dataOut_32 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_31 on net dataOut_31 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_30 on net dataOut_30 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_29 on net dataOut_29 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_28 on net dataOut_28 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_27 on net dataOut_27 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_26 on net dataOut_26 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_25 on net dataOut_25 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_24 on net dataOut_24 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_23 on net dataOut_23 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_22 on net dataOut_22 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_21 on net dataOut_21 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_20 on net dataOut_20 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_19 on net dataOut_19 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_18 on net dataOut_18 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_17 on net dataOut_17 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_16 on net dataOut_16 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_15 on net dataOut_15 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_14 on net dataOut_14 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_13 on net dataOut_13 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_12 on net dataOut_12 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_11 on net dataOut_11 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_10 on net dataOut_10 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_9 on net dataOut_9 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_8 on net dataOut_8 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_7 on net dataOut_7 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_6 on net dataOut_6 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_5 on net dataOut_5 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_4 on net dataOut_4 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_3 on net dataOut_3 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_2 on net dataOut_2 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: directcache.v(63): tristate driver dataOut_1 on net dataOut_1 has its enable tied to GND (module directCache)  @W:"u:\lab5\directcache.v":63:14:63:21
@W: upedge_detector.v(18): Removing sequential instance myUpedger.D1 of view:PrimLib.dff(prim) because there are no references to its outputs  @W:"u:\lab5\upedge_detector.v":18:3:18:9
@W: upedge_detector.v(18): Removing sequential instance myUpedger.D0 of view:PrimLib.dff(prim) because there are no references to its outputs  @W:"u:\lab5\upedge_detector.v":18:3:18:9

541 warnings