I plan to be in after 6 pm, probably 8pm at latest. I'll stay in till 2 or 3 am.
Jason, if you'd like I can modify memController to feed your caches the 8 word burst when u get the read enable signal. Basically instead of having it on for 8 cycles, it'll be on just for 1 cycle as data is valid.
However, if you could modify your cache specs, so that data won't appear for an address till the next clock edge WITH the readEnable signal, I think that would be a better spec, because the problem we're facing is during a stall that takes two cycles the cache is outputting the correct address on the 2nd cycle of stall, and changing the very next cycle so we're losing an instruction.
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I plan to be in after 6 pm, probably 8pm at latest. I'll stay in till 2 or 3 am.
Jason, if you'd like I can modify memController to feed your caches the 8 word burst when u get the read enable signal. Basically instead of having it on for 8 cycles, it'll be on just for 1 cycle as data is valid.
However, if you could modify your cache specs, so that data won't appear for an address till the next clock edge WITH the readEnable signal, I think that would be a better spec, because the problem we're facing is during a stall that takes two cycles the cache is outputting the correct address on the 2nd cycle of stall, and changing the very next cycle so we're losing an instruction.
I will be back later when Alan comes in.