Our current status on the board is not too bright. Using our fixed buffers we cannot get past any stalls (including breaks or misses). We are also losing the first instruction. Lots of suspicion is in the buffer that we use (since the async fifos can get by it). We might try using the asyncs while someone works on getting buffer behavior equal to that of the coregen'ed async fifos.
It also seems like the datapath is not working on the board in single step or full speed.
We will try to finish this after our 174 hw. No guarentees.
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Our current status on the board is not too bright. Using our fixed buffers we cannot get past any stalls (including breaks or misses). We are also losing the first instruction. Lots of suspicion is in the buffer that we use (since the async fifos can get by it). We might try using the asyncs while someone works on getting buffer behavior equal to that of the coregen'ed async fifos.
It also seems like the datapath is not working on the board in single step or full speed.
We will try to finish this after our 174 hw. No guarentees.