Here's a status update of the processor. We have fixed all known bugs in the datapath (not the cache) and it is now ready for heavier testing focusing on things like collision of inst and datamem missing, cache misses as a whole, watching the write buffer and its behavior.
We do not anticipate many problems with these as we have already run it through corner.s (minor modifications...damit...) and it seems to be working correctly as long as the ram clock is faster than the processor clock by less than 25x the ram clock.
We should begin integration testing on the board just to make sure that everything works in simulation like it does on the board. There is a possibility of timing problems as demonstrated in simulation. Thus there will be some work in making our simulations model that of real life much closer (including clock times).
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what exactly doesn't work? When we do single stepping mode, it's going to be several million times faster, how will that work. We need some handshaking signals to cross the clock boundaries.
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At 33x in simulation, we were losing a delay slot of a beq somewhere around 29f or something I don't remember exactly what. If you'd like to take a look at it, you can see exactly what doesn't work. Just simulate it yourself and search for it.
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Hey all,
Here's a status update of the processor. We have fixed all known bugs in the datapath (not the cache) and it is now ready for heavier testing focusing on things like collision of inst and datamem missing, cache misses as a whole, watching the write buffer and its behavior.
We do not anticipate many problems with these as we have already run it through corner.s (minor modifications...damit...) and it seems to be working correctly as long as the ram clock is faster than the processor clock by less than 25x the ram clock.
We should begin integration testing on the board just to make sure that everything works in simulation like it does on the board. There is a possibility of timing problems as demonstrated in simulation. Thus there will be some work in making our simulations model that of real life much closer (including clock times).
As clarification, Mike had to modify cpu.v such that during a stall, we fed PC into instmem as opposed to newPC.
Tomorrow, I will attempt to bring it to board. Brian, hopefully you can write the test code that tries to break the cache using mips code.
what exactly doesn't work? When we do single stepping mode, it's going to be several million times faster, how will that work. We need some handshaking signals to cross the clock boundaries.
At 33x in simulation, we were losing a delay slot of a beq somewhere around 29f or something I don't remember exactly what. If you'd like to take a look at it, you can see exactly what doesn't work. Just simulate it yourself and search for it.