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From: Gerald Z. <ri...@us...> - 2003-05-21 12:23:19
|
Update of /cvsroot/dso/FPGA/tb In directory sc8-pr-cvs1:/tmp/cvs-serv28799/tb Modified Files: tb_Datapath.vhd Log Message: Index: tb_Datapath.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/tb/tb_Datapath.vhd,v retrieving revision 1.7 retrieving revision 1.8 diff -C2 -d -r1.7 -r1.8 *** tb_Datapath.vhd 14 May 2003 08:38:00 -0000 1.7 --- tb_Datapath.vhd 21 May 2003 12:23:16 -0000 1.8 *************** *** 376,380 **** -- TODO: write this test, it is now possible with the signal "MAM_PP" ! assert false report "Ready" severity FAILURE; end process p_Test; --- 376,380 ---- -- TODO: write this test, it is now possible with the signal "MAM_PP" ! report "END of Test (don't care about further warnings!)" severity NOTE; end process p_Test; |
From: Gerald Z. <ri...@us...> - 2003-05-21 12:23:18
|
Update of /cvsroot/dso/FPGA/src In directory sc8-pr-cvs1:/tmp/cvs-serv28799/src Modified Files: Latch_A_rtl.vhd Latch_D_rtl.vhd Log Message: Index: Latch_A_rtl.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/src/Latch_A_rtl.vhd,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** Latch_A_rtl.vhd 25 Mar 2003 09:40:59 -0000 1.4 --- Latch_A_rtl.vhd 21 May 2003 12:23:15 -0000 1.5 *************** *** 7,11 **** -- Date of Creation: 26-02-2003 -- ! -- Description: Latch for analog input - rtl design -- ------------------------------------------------------------------------------- --- 7,11 ---- -- Date of Creation: 26-02-2003 -- ! -- Description: Latch for analog input - rtl design -- ------------------------------------------------------------------------------- *************** *** 42,63 **** -- outputs: Min_o, Avg_o, Max_o p_Latch_A: process (Clk, Reset) - variable MinStore : std_logic_vector(AnalogWidth -1 downto 0); - variable AvgStore : std_logic_vector(AverageWidth-1 downto 0); - variable MaxStore : std_logic_vector(AnalogWidth -1 downto 0); begin -- process p_Latch_A if Reset = '0' then -- asynchronous reset (active low) ! MinStore := (others => '0'); ! AvgStore := (others => '0'); ! MaxStore := (others => '0'); elsif Clk'event and Clk = '1' then -- rising clock edge if Latch_i = '1' then ! MinStore := Min_i; ! AvgStore := Avg_i; ! MaxStore := Max_i; end if; end if; - Min_o <= MinStore; - Avg_o <= AvgStore; - Max_o <= MaxStore; end process p_Latch_A; --- 42,57 ---- -- outputs: Min_o, Avg_o, Max_o p_Latch_A: process (Clk, Reset) begin -- process p_Latch_A if Reset = '0' then -- asynchronous reset (active low) ! Min_o <= (others => '0'); ! Avg_o <= (others => '0'); ! Max_o <= (others => '0'); elsif Clk'event and Clk = '1' then -- rising clock edge if Latch_i = '1' then ! Min_o <= Min_i; ! Avg_o <= Avg_i; ! Max_o <= Max_i; end if; end if; end process p_Latch_A; Index: Latch_D_rtl.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/src/Latch_D_rtl.vhd,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** Latch_D_rtl.vhd 1 Apr 2003 09:13:43 -0000 1.4 --- Latch_D_rtl.vhd 21 May 2003 12:23:15 -0000 1.5 *************** *** 1,14 **** ------------------------------------------------------------------------------- -- ! -- Author: Sobhi Maher -- Filename: Latch_D_rtl.vhd -- -- Date of Creation: 26-02-2003 -- ! -- -- ------------------------------------------------------------------------------- -- ! -- Copyright (C) 2003 Sobhi Maher -- -- This program is free software; you can redistribute it and/or modify --- 1,15 ---- ------------------------------------------------------------------------------- -- ! -- Author: Gerald Zach ! -- -- Filename: Latch_D_rtl.vhd -- -- Date of Creation: 26-02-2003 -- ! -- Description: Latch for Digital Input - rtl design -- ------------------------------------------------------------------------------- -- ! -- Copyright (C) 2003 Gerald Zach -- -- This program is free software; you can redistribute it and/or modify *************** *** 38,56 **** -- inputs : Clk, Reset, Min_i, Max_i, Latch_i -- outputs: Min_o,Max_o ! Seq0: process (Clk, Reset) ! variable MinValue : std_logic_vector(DigitalWidth-1 downto 0); -- last minimum is stored here ! variable MaxValue : std_logic_vector(DigitalWidth-1 downto 0); -- last maximum is stored here ! begin -- process Seq0 if Reset = '0' then -- asynchronous reset (active low) ! MinValue := (others => '0'); ! MaxValue := (others => '0'); elsif Clk'event and Clk = '1' then -- rising clock edge if Latch_i = '1' then ! MinValue := Min_i; ! MaxValue := Max_i; end if; end if; ! Min_o <= MinValue; ! Max_o <= MaxValue; ! end process Seq0; end rtl; --- 39,53 ---- -- inputs : Clk, Reset, Min_i, Max_i, Latch_i -- outputs: Min_o,Max_o ! p_Latch_D: process (Clk, Reset) ! begin -- process p_Latch_D if Reset = '0' then -- asynchronous reset (active low) ! Min_o <= (others => '0'); ! Max_o <= (others => '0'); elsif Clk'event and Clk = '1' then -- rising clock edge if Latch_i = '1' then ! Min_o <= Min_i; ! Max_o <= Max_i; end if; end if; ! end process p_Latch_D; end rtl; |
From: Johann G. <han...@us...> - 2003-05-18 20:00:34
|
Update of /cvsroot/dso/FPGA/Synplify In directory sc8-pr-cvs1:/tmp/cvs-serv5204/Synplify Modified Files: project.prd project.prj Log Message: Synplify simulations. Index: project.prd =================================================================== RCS file: /cvsroot/dso/FPGA/Synplify/project.prd,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** project.prd 9 Apr 2003 11:43:54 -0000 1.3 --- project.prd 18 May 2003 20:00:29 -0000 1.4 *************** *** 2,6 **** #-- Version 7.0.3 #-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prd ! #-- Written on Wed Apr 9 13:41:37 2003 # --- 2,6 ---- #-- Version 7.0.3 #-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prd ! #-- Written on Wed May 14 12:13:01 2003 # Index: project.prj =================================================================== RCS file: /cvsroot/dso/FPGA/Synplify/project.prj,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** project.prj 9 Apr 2003 11:43:54 -0000 1.3 --- project.prj 18 May 2003 20:00:30 -0000 1.4 *************** *** 2,6 **** #-- Version 7.0.3 #-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prj ! #-- Written on Wed Apr 9 13:41:37 2003 --- 2,6 ---- #-- Version 7.0.3 #-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prj ! #-- Written on Wed May 14 12:13:01 2003 *************** *** 81,85 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 81,84 ---- *************** *** 115,119 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 114,117 ---- *************** *** 149,153 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 147,150 ---- *************** *** 183,187 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 180,183 ---- *************** *** 217,221 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 213,216 ---- *************** *** 251,255 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 246,249 ---- *************** *** 285,289 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 279,282 ---- *************** *** 319,323 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 312,315 ---- *************** *** 353,357 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 345,348 ---- *************** *** 387,391 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 378,381 ---- *************** *** 421,425 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 411,414 ---- *************** *** 455,459 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 444,447 ---- *************** *** 489,493 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 477,480 ---- *************** *** 523,527 **** set_option -disable_io_insertion 0 set_option -pipe 0 - set_option -modular 0 set_option -retiming 0 --- 510,513 ---- *************** *** 535,537 **** #set result format/file last project -result_file "PP_Clk/rev_1.edf" ! impl -active "PP_Clk" --- 521,523 ---- #set result format/file last project -result_file "PP_Clk/rev_1.edf" ! impl -active "DEMUX_PP" |
From: Johann G. <han...@us...> - 2003-05-15 08:44:00
|
Update of /cvsroot/dso/FPGA/dc In directory sc8-pr-cvs1:/tmp/cvs-serv15764 Modified Files: command.log Log Message: Index: command.log =================================================================== RCS file: /cvsroot/dso/FPGA/dc/command.log,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** command.log 15 May 2003 07:57:34 -0000 1.1 --- command.log 15 May 2003 08:00:27 -0000 1.2 *************** *** 698,699 **** --- 698,700 ---- } } + elaborate main_module -update |
From: Johann G. <han...@us...> - 2003-05-15 08:32:01
|
Update of /cvsroot/dso/FPGA/dc/scr In directory sc8-pr-cvs1:/tmp/cvs-serv15764/scr Added Files: synth_dc.scr Log Message: --- NEW FILE: synth_dc.scr --- /* ----------------------------------------------------- */ /* This is the synthesis script for the fulladder design */ /* ----------------------------------------------------- */ /* write some informative data to the log file */ sh date sh hostname /* main module of our design */ main_module = datapath /* file list of our design, without ".vhd" extension */ file_list = {Avg_A_, \ Avg_A_rtl, \ DEMUX_PP_, \ DEMUX_PP_rtl, \ Datapath_, \ Datapath_struc, \ Join_Avg_, \ Join_Avg_struc, \ Join_MinMax_, \ Join_MinMax_struc, \ Latch_A_, \ Latch_A_rtl, \ Latch_D_, \ Latch_D_rtl, \ MAM_A_, \ MAM_A_P_, \ MAM_A_P_struc, \ MAM_A_struc, \ MAM_D_, \ MAM_D_P_, \ MAM_D_P_struc, \ MAM_D_struc, \ MUX_4_N_, \ MUX_4_N_rtl, \ MUX_AD_, \ MUX_AD_struc, \ MUX_N_1_, \ MUX_N_1_rtl, \ MUX_RAM_, \ MUX_RAM_rtl, \ MUX_uC_, \ MUX_uC_rtl, \ Max_A_, \ Max_A_rtl, \ Max_D_, \ Max_D_rtl, \ Min_A_, \ Min_A_rtl, \ Min_D_, \ Min_D_rtl, \ PP_Clk_, \ PP_Clk_rtl, \ types_p } /* directory structure variables used later in the script */ db_area = "./db/" vhd_area = "../src/" report_area = "./reports/" script_area = "./scr/" /* analyze every VHDL file only for syntax */ foreach (member, file_list) { analyze -format vhdl vhd_area + member + ".vhd" if (dc_shell_status == 0) { echo "ANALYSIS ERROR OR FILE " member " NOT FOUND" quit } } elaborate main_module -update check_design write -f db -h -o db_area + main_module + "_pre.db" /* every net gets its unique name */ uniquify /* remove hierarchy from design */ ungroup -all -flatten /* set main module for following commands */ current_design = main_module /* setup design parameters */ set_wire_load "0to50" -library MTC45000_WL_WORST set_operating_conditions WCCOM set_driving_cell -cell IV -library MTC45000 all_inputs() set_load 3.5 * load_of(MTC45000/IV/A) all_outputs() set_load 3.5 * load_of(MTC45000/IV/A) all_inputs() /* Compile the design and write database */ /* check if everything is setup correctly */ check_design /* compile the design and optimize, map to target technology */ compile /* write out the (optimized) database */ write -f db -h -o db_area + main_module + ".db" check_design /* Generate reports */ report_area > report_area + main_module + ".area" report_timing > report_area + main_module + ".time" report_cell > report_area + main_module + ".cell" sh date quit |
From: Johann G. <han...@us...> - 2003-05-15 08:15:47
|
Update of /cvsroot/dso/FPGA/dc In directory sc8-pr-cvs1:/tmp/cvs-serv21152 Modified Files: command.log view_command.log Log Message: Index: command.log =================================================================== RCS file: /cvsroot/dso/FPGA/dc/command.log,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** command.log 15 May 2003 08:00:27 -0000 1.2 --- command.log 15 May 2003 08:15:44 -0000 1.3 *************** *** 1,4 **** ! /* krypton -- Thu May 15 09:56:17 2003 ! Initial dc_shell Variable Values */ --- 1,4 ---- ! /* krypton -- Thu May 15 10:05:49 2003 ! Initial design_analyzer Variable Values */ *************** *** 6,32 **** _bs_suppress_errors = {"PWR-18", "OPT-931", "OPT-932"} _bs_valid_program = "true" - acs_area_report_suffix = "area" - acs_bs_exec = "" - acs_budget_output_file_suffix = "btcl.out" - acs_budget_script_file_suffix = "btcl" - acs_budgeted_cstr_suffix = "con" - acs_compile_script_suffix = "autoscr" - acs_constraint_file_suffix = "con" - acs_cstr_report_suffix = "cstr" - acs_db_suffix = "db" - acs_dc_exec = "" - acs_global_user_compile_strategy_script = "default.compile" - acs_log_file_suffix = "log" - acs_makefile_name = "Makefile" - acs_num_parallel_jobs = "1" - acs_override_script_suffix = "scr" - acs_qor_report_suffix = "qor" - acs_script_mode = "dcsh" - acs_timing_report_suffix = "tim" - acs_tr_exec = "" - acs_use_lsf = "false" - acs_user_budgeting_script = "budget.scr" - acs_user_compile_strategy_script_suffix = "compile" - acs_work_dir = "/a/ursus/chip004/hansi/FPGA/dc" atpg_bidirect_output_only = "false" atpg_test_asynchronous_pins = "true" --- 6,9 ---- *************** *** 71,75 **** change_names_dont_change_bus_members = "false" change_names_update_inst_tree = "true" - check_error_list = {"CMD-004", "CMD-006", "CMD-007", "CMD-008", "CMD-009", "CMD-010", "CMD-011", "CMD-012", "CMD-014", "CMD-015", "CMD-016", "CMD-019", "CMD-026", "CMD-031", "CMD-037", "DB-1", "DCSH-11", "DES-001", "FILE-1", "FILE-2", "FILE-3", "FILE-4", "LINK-5", "LINK-7", "LINT-7", "LINT-20", "LNK-023", "OPT-100", "OPT-101", "OPT-102", "OPT-114", "OPT-124", "OPT-127", "OPT-128", "OPT-155", "OPT-157", "OPT-181", "OPT-462", "UI-11", "UI-14", "UI-15", "UI-16", "UI-17", "UI-19", "UI-20", "UI-21", "UI-22", "UI-23", "UI-40", "UI-41", "UID-4", "UID-6", "UID-7", "UID-8", "UID-9", "UID-13", "UID-14", "UID-15", "UID-19", "UID-20", "UID-25", "UID-27", "UID-28", "UID-29", "UID-30", "UID-32", "UID-58", "UID-87", "UID-103", "UID-109", "UID-270", "UID-272", "UID-403", "UID-440", "UID-444", "UIO-2", "UIO-3", "UIO-4", "UIO-25", "UIO-65", "UIO-66", "UIO-75", "UIO-94", "UIO-95", "EQN-6", "EQN-11", "EQN-15", "EQN-16", "EQN-18", "EQN-20"} command_log_file = "./command.log" company = "Vienna University of Technology" --- 48,51 ---- *************** *** 132,138 **** dc_shell_mode = "default" dc_shell_status = 1 - default_input_delay = 30.000000 default_name_rules = "" - default_output_delay = 30.000000 default_port_connection_class = "universal" default_schematic_options = "-size infinite" --- 108,112 ---- *************** *** 399,402 **** --- 373,377 ---- sh_enable_page_mode = "true" sh_source_uses_search_path = "true" + shell_prompt = "design_analyzer> " single_group_per_sheet = "false" site_info_file = "/home/synopsys/9910/admin/license/site_info" *************** *** 539,542 **** --- 514,518 ---- view_background = "black" view_cache_images = "true" + view_clear_whole_area_on_delete = "false" view_command_log_file = "./view_command.log" view_command_win_max_lines = 1000 *************** *** 547,555 **** --- 523,537 ---- view_error_window_count = 6 view_execute_script_suffix = {".script", ".scr", ".dcs", ".dcv", ".dc", ".con"} + view_image_cache_options = 1 view_info_search_cmd = "/home/synopsys/9910/infosearch/scripts/InfoSearch" + view_linear_box_search_percentage = 95 + view_linear_line_search_percentage = 85 view_log_file = "" + view_max_image_size_to_cache = 175 view_on_line_doc_cmd = "/home/synopsys/9910/sold" view_read_file_suffix = {"db", "gdb", "sdb", "edif", "eqn", "fnc", "lsi", "mif", "NET", "pla", "st", "tdl", "v", "vhd", "vhdl", "xnf"} view_script_submenu_items = {"DA to SGE Transfer", "write_sge"} + view_set_draw_interrupt_limit = 500 + view_set_select_interrupt_limit = 200 view_tools_menu_items = {} view_use_small_cursor = "" *************** *** 567,573 **** --- 549,560 ---- write_test_scan_check_file_naming_style = "%s_schk.%s" write_test_vector_file_naming_style = "%s_%d.%s" + x11_display_string = "krypton:12.0" + x11_is_color = "true" x11_set_cursor_background = "" x11_set_cursor_foreground = "" x11_set_cursor_number = -1 + x11_vendor_release_number = 7000 + x11_vendor_string = "Humming" + x11_vendor_version_number = 11 xnfin_dff_clock_enable_pin_name = "CE" xnfin_dff_clock_pin_name = "C" *************** *** 585,589 **** ! /* Initial dc_shell Aliases */ --- 572,576 ---- ! /* Initial design_analyzer Aliases */ *************** *** 630,700 **** ! /* dc_shell Command Log */ ! /* ----------------------------------------------------- */ ! /* This is the synthesis script for the fulladder design */ ! /* ----------------------------------------------------- */ ! /* write some informative data to the log file */ ! sh date ! sh hostname ! /* main module of our design */ ! main_module = datapath ! /* file list of our design, without ".vhd" extension */ ! file_list = {Avg_A_, \ ! Avg_A_rtl, \ ! DEMUX_PP_, \ ! DEMUX_PP_rtl, \ ! Datapath_, \ ! Datapath_struc, \ ! Join_Avg_, \ ! Join_Avg_struc, \ ! Join_MinMax_, \ ! Join_MinMax_struc, \ ! Latch_A_, \ ! Latch_A_rtl, \ ! Latch_D_, \ ! Latch_D_rtl, \ ! MAM_A_, \ ! MAM_A_P_, \ ! MAM_A_P_struc, \ ! MAM_A_struc, \ ! MAM_D_, \ ! MAM_D_P_, \ ! MAM_D_P_struc, \ ! MAM_D_struc, \ ! MUX_4_N_, \ ! MUX_4_N_rtl, \ ! MUX_AD_, \ ! MUX_AD_struc, \ ! MUX_N_1_, \ ! MUX_N_1_rtl, \ ! MUX_RAM_, \ ! MUX_RAM_rtl, \ ! MUX_uC_, \ ! MUX_uC_rtl, \ ! Max_A_, \ ! Max_A_rtl, \ ! Max_D_, \ ! Max_D_rtl, \ ! Min_A_, \ ! Min_A_rtl, \ ! Min_D_, \ ! Min_D_rtl, \ ! PP_Clk_, \ ! PP_Clk_rtl, \ ! types_p } ! /* directory structure variables used later in the script */ ! db_area = "./db/" ! vhd_area = "../src/" ! report_area = "./reports/" ! script_area = "./scr/" ! /* analyze every VHDL file only for syntax */ ! foreach (member, file_list) { ! analyze -format vhdl vhd_area + member + ".vhd" ! if (dc_shell_status == 0) { ! echo "ANALYSIS ERROR OR FILE " member " NOT FOUND" ! quit ! } ! } ! elaborate main_module -update --- 617,639 ---- ! /* design_analyzer Command Log */ ! read -format db {"/a/ursus/chip004/hansi/FPGA/dc/db/datapath_pre.db"} ! create_schematic -size infinite -gen_database ! create_schematic -size infinite -symbol_view ! create_schematic -size infinite -hier_view ! create_schematic -size infinite -schematic_view ! current_instance "i_MUX_RAM" ! create_schematic -size infinite -symbol_view -reference ! create_schematic -size infinite -hier_view -reference ! create_schematic -size infinite -schematic_view -reference ! current_instance ".." ! current_instance "i_MAM_D_Dig" ! create_schematic -size infinite -symbol_view -reference ! create_schematic -size infinite -hier_view -reference ! create_schematic -size infinite -schematic_view -reference ! current_instance ".." ! current_instance "i_MAM_A_Ch1" ! create_schematic -size infinite -symbol_view -reference ! create_schematic -size infinite -hier_view -reference Index: view_command.log =================================================================== RCS file: /cvsroot/dso/FPGA/dc/view_command.log,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** view_command.log 15 May 2003 07:57:34 -0000 1.1 --- view_command.log 15 May 2003 08:15:44 -0000 1.2 *************** *** 17,24 **** Copyright (c) 1988-1999 by Synopsys, Inc. ALL RIGHTS RESERVED ! design_analyzer> read -format db {"/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db"} ! Loading db file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db' ! Current design is now '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder' ! {"fulladder", "or_gate", "halfadder"} design_analyzer> create_schematic -size infinite -gen_database Loading db file '/home/synopsys/9910/libraries/syn/generic.sdb' --- 17,24 ---- Copyright (c) 1988-1999 by Synopsys, Inc. ALL RIGHTS RESERVED ! design_analyzer> read -format db {"/a/ursus/chip004/hansi/FPGA/dc/db/datapath_pre.db"} ! Loading db file '/a/ursus/chip004/hansi/FPGA/dc/db/datapath_pre.db' ! Current design is now '/a/ursus/chip004/hansi/FPGA/dc/db/datapath_pre.db:Datapath' ! {"Datapath", "MAM_D_P_DigitalWidth32", "MAM_A_P_AnalogWidth10_AverageWidth36", "MUX_RAM_RAM_Width72", "MUX_AD_AnalogWidth10_AverageWidth36_DigitalWidth32_RAM_Width72", "Join_Avg_AverageWidth36_RAM_Width72", "Join_MinMax_AnalogWidth10_DigitalWidth32_RAM_Width72", "MAM_D_DigitalWidth32", "MAM_A_AnalogWidth10_AverageWidth36", "MUX_uC", "PP_Clk"} design_analyzer> create_schematic -size infinite -gen_database Loading db file '/home/synopsys/9910/libraries/syn/generic.sdb' *************** *** 30,45 **** Loading db file '/home/synopsys/9910/libraries/syn/gtech.db' Loading db file '/home/synopsys/9910/libraries/syn/standard.sldb' create_schematic -size infinite -symbol_view 1 design_analyzer> create_schematic -size infinite -hier_view 1 design_analyzer> create_schematic -size infinite -schematic_view ! Generating schematic for design: fulladder ! The schematic for design 'fulladder' has 1 page(s). 1 ! design_analyzer> current_instance "i_halfadder2" ! Current instance is '/fulladder/i_halfadder2'. ! "/fulladder/i_halfadder2" design_analyzer> create_schematic -size infinite -symbol_view -reference 1 --- 30,154 ---- Loading db file '/home/synopsys/9910/libraries/syn/gtech.db' Loading db file '/home/synopsys/9910/libraries/syn/standard.sldb' + Information: Building the design 'Latch_A' instantiated from design 'Datapath' with + the parameters "AnalogWidth => 10, AverageWidth => 36". (HDL-193) + Reading in the Synopsys vhdl primitives. + Error: Tried to use a synchronized value + in call to '<=' + called from Latch_A_AnalogWidth10_AverageWidth36 line 59 in file '/a/ursus/chip004/hansi/FPGA/src/Latch_A_rtl.vhd' (HDL-107) + Error: 'Latch_A' was not identified as a synthetic library module + and could not be successfully elaborated from design library 'work'. (LINK-10) + Warning: Unable to resolve reference 'Latch_A_AnalogWidth10_AverageWidth36' in 'Datapath'. (LINK-5) + Information: Building the design 'Latch_D' instantiated from design 'Datapath' with + the parameters "DigitalWidth => 32". (HDL-193) + Error: Tried to use a synchronized value + in call to '<=' + called from Latch_D_DigitalWidth32 line 53 in file '/a/ursus/chip004/hansi/FPGA/src/Latch_D_rtl.vhd' (HDL-107) + Error: 'Latch_D' was not identified as a synthetic library module + and could not be successfully elaborated from design library 'work'. (LINK-10) + Warning: Unable to resolve reference 'Latch_D_DigitalWidth32' in 'Datapath'. (LINK-5) + Information: Building the design 'DEMUX_PP' instantiated from design 'Datapath' with + the parameters "AnalogWidth => 10, AverageWidth => 36, DigitalWidth => 32, RAM_Width => 72". (HDL-193) + Error: Can't determine type of aggregate or concat + in routine DEMUX_PP_AnalogWidth10_AverageWidth36_DigitalWidth32_RAM_Width72 line 64 in file '/a/ursus/chip004/hansi/FPGA/src/DEMUX_PP_rtl.vhd' (HDL-123) + Error: 'DEMUX_PP' was not identified as a synthetic library module + and could not be successfully elaborated from design library 'work'. (LINK-10) + Warning: Unable to resolve reference 'DEMUX_PP_AnalogWidth10_AverageWidth36_DigitalWidth32_RAM_Width72' in 'Datapath'. (LINK-5) + Information: Building the design 'Min_A' instantiated from design 'MAM_A_AnalogWidth10_AverageWidth36' with + the parameters "Width => 10". (HDL-193) + Error: Tried to use a synchronized value + in call to '<=' + called from Min_A_Width10 line 55 in file '/a/ursus/chip004/hansi/FPGA/src/Min_A_rtl.vhd' (HDL-107) + Error: Additional errors suppressed. + See the Command Window for a full error message listing. (MOUI-21) + Error: 'Min_A' was not identified as a synthetic library module + and could not be successfully elaborated from design library 'WORK'. (LINK-10) + Warning: Unable to resolve reference 'Min_A_Width10' in 'datapath_pre.db:MAM_A_AnalogWidth10_AverageWidth36'. (LINK-5) + Information: Building the design 'Avg_A' instantiated from design 'MAM_A_AnalogWidth10_AverageWidth36' with + the parameters "WidthIn => 10, WidthOut => 36". (HDL-193) + Error: Can't determine type of aggregate or concat + in routine Avg_A_WidthIn10_WidthOut36 line 57 in file '/a/ursus/chip004/hansi/FPGA/src/Avg_A_rtl.vhd' (HDL-123) + Error: 'Avg_A' was not identified as a synthetic library module + and could not be successfully elaborated from design library 'WORK'. (LINK-10) + Warning: Unable to resolve reference 'Avg_A_WidthIn10_WidthOut36' in 'datapath_pre.db:MAM_A_AnalogWidth10_AverageWidth36'. (LINK-5) + Information: Building the design 'Max_A' instantiated from design 'MAM_A_AnalogWidth10_AverageWidth36' with + the parameters "Width => 10". (HDL-193) + Error: Tried to use a synchronized value + in call to '<=' + called from Max_A_Width10 line 55 in file '/a/ursus/chip004/hansi/FPGA/src/Max_A_rtl.vhd' (HDL-107) + Error: 'Max_A' was not identified as a synthetic library module + and could not be successfully elaborated from design library 'WORK'. (LINK-10) + Warning: Unable to resolve reference 'Max_A_Width10' in 'datapath_pre.db:MAM_A_AnalogWidth10_AverageWidth36'. (LINK-5) + Information: Building the design 'Min_D' instantiated from design 'MAM_D_DigitalWidth32' with + the parameters "Width => 32". (HDL-193) + Error: Tried to use a synchronized value + in call to '<=' + called from Min_D_Width32 line 58 in file '/a/ursus/chip004/hansi/FPGA/src/Min_D_rtl.vhd' (HDL-107) + Error: 'Min_D' was not identified as a synthetic library module + and could not be successfully elaborated from design library 'WORK'. (LINK-10) + Warning: Unable to resolve reference 'Min_D_Width32' in 'datapath_pre.db:MAM_D_DigitalWidth32'. (LINK-5) + Information: Building the design 'Max_D' instantiated from design 'MAM_D_DigitalWidth32' with + the parameters "Width => 32". (HDL-193) + Error: Tried to use a synchronized value + in call to '<=' + called from Max_D_Width32 line 58 in file '/a/ursus/chip004/hansi/FPGA/src/Max_D_rtl.vhd' (HDL-107) + Error: 'Max_D' was not identified as a synthetic library module + and could not be successfully elaborated from design library 'WORK'. (LINK-10) + Warning: Unable to resolve reference 'Max_D_Width32' in 'datapath_pre.db:MAM_D_DigitalWidth32'. (LINK-5) + Information: Building the design 'Min_A' instantiated from design 'MAM_A_P_AnalogWidth10_AverageWidth36' with + the parameters "Width => 10". (HDL-193) + Error: Tried to use a synchronized value + in call to '<=' + called from Min_A_Width10 line 55 in file '/a/ursus/chip004/hansi/FPGA/src/Min_A_rtl.vhd' (HDL-107) + Error: 'Min_A' was not identified as a synthetic library module + and could not be successfully elaborated from design library 'WORK'. (LINK-10) + Warning: Unable to resolve reference 'Min_A_Width10' in 'datapath_pre.db:MAM_A_P_AnalogWidth10_AverageWidth36'. (LINK-5) + Information: Building the design 'Avg_A' instantiated from design 'MAM_A_P_AnalogWidth10_AverageWidth36' with + the parameters "WidthIn => 36, WidthOut => 36". (HDL-193) + Error: Tried to use a synchronized value + in call to '<=' + called from Avg_A_WidthIn36_WidthOut36 line 64 in file '/a/ursus/chip004/hansi/FPGA/src/Avg_A_rtl.vhd' (HDL-107) + Error: 'Avg_A' was not identified as a synthetic library module + and could not be successfully elaborated from design library 'WORK'. (LINK-10) + Warning: Unable to resolve reference 'Avg_A_WidthIn36_WidthOut36' in 'datapath_pre.db:MAM_A_P_AnalogWidth10_AverageWidth36'. (LINK-5) + Information: Building the design 'Max_A' instantiated from design 'MAM_A_P_AnalogWidth10_AverageWidth36' with + the parameters "Width => 10". (HDL-193) + Error: Tried to use a synchronized value + in call to '<=' + called from Max_A_Width10 line 55 in file '/a/ursus/chip004/hansi/FPGA/src/Max_A_rtl.vhd' (HDL-107) + Error: 'Max_A' was not identified as a synthetic library module + and could not be successfully elaborated from design library 'WORK'. (LINK-10) + Warning: Unable to resolve reference 'Max_A_Width10' in 'datapath_pre.db:MAM_A_P_AnalogWidth10_AverageWidth36'. (LINK-5) + Information: Building the design 'Min_D' instantiated from design 'MAM_D_P_DigitalWidth32' with + the parameters "Width => 32". (HDL-193) + Error: Tried to use a synchronized value + in call to '<=' + called from Min_D_Width32 line 58 in file '/a/ursus/chip004/hansi/FPGA/src/Min_D_rtl.vhd' (HDL-107) + Error: 'Min_D' was not identified as a synthetic library module + and could not be successfully elaborated from design library 'work'. (LINK-10) + Warning: Unable to resolve reference 'Min_D_Width32' in 'datapath_pre.db:MAM_D_P_DigitalWidth32'. (LINK-5) + Information: Building the design 'Max_D' instantiated from design 'MAM_D_P_DigitalWidth32' with + the parameters "Width => 32". (HDL-193) + Error: Tried to use a synchronized value + in call to '<=' + called from Max_D_Width32 line 58 in file '/a/ursus/chip004/hansi/FPGA/src/Max_D_rtl.vhd' (HDL-107) + Error: 'Max_D' was not identified as a synthetic library module + and could not be successfully elaborated from design library 'work'. (LINK-10) + Warning: Unable to resolve reference 'Max_D_Width32' in 'datapath_pre.db:MAM_D_P_DigitalWidth32'. (LINK-5) create_schematic -size infinite -symbol_view + Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341) 1 design_analyzer> create_schematic -size infinite -hier_view + Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341) 1 design_analyzer> create_schematic -size infinite -schematic_view ! Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341) ! Generating schematic for design: Datapath ! The schematic for design 'Datapath' has 1 page(s). 1 ! design_analyzer> current_instance "i_MUX_RAM" ! Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341) ! Current instance is '/Datapath/i_MUX_RAM'. ! "/Datapath/i_MUX_RAM" design_analyzer> create_schematic -size infinite -symbol_view -reference 1 *************** *** 47,127 **** 1 design_analyzer> create_schematic -size infinite -schematic_view -reference ! Generating schematic for design: halfadder ! The schematic for design 'halfadder' has 1 page(s). 1 - design_analyzer> read -format db {"/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db"} - Loading db file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db' - Current design is now '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder' - {"fulladder"} - design_analyzer> create_schematic -size infinite -gen_database - 1 - design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder" - Current design is 'fulladder'. - {"fulladder"} - design_analyzer> current_instance "i_halfadder2" - Current instance is '/fulladder/i_halfadder2'. - "/fulladder/i_halfadder2" - design_analyzer> read -format db {"/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db"} - Loading db file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db' - Warning: Overwriting design file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db'. (DDB-24) - Current design is now '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder' - {"fulladder"} - design_analyzer> create_schematic -size infinite -gen_database - 1 - design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder" - Current design is 'fulladder'. - {"fulladder"} - design_analyzer> current_instance "i_halfadder2" - Current instance is '/fulladder/i_halfadder2'. - "/fulladder/i_halfadder2" design_analyzer> current_instance ".." ! Current instance is the top-level of design 'fulladder'. "" ! design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder" ! Current design is 'fulladder'. ! {"fulladder"} ! design_analyzer> reset_design ! Resetting current design 'fulladder' ! 1 ! design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder" ! Current design is 'fulladder'. ! {"fulladder"} ! design_analyzer> reset_design ! Resetting current design 'fulladder' ! 1 ! design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:halfadder" ! Current design is 'halfadder'. ! {"halfadder"} ! design_analyzer> reset_design ! Resetting current design 'halfadder' ! 1 ! design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:or_gate" ! Current design is 'or_gate'. ! {"or_gate"} ! design_analyzer> reset_design ! Resetting current design 'or_gate' 1 ! design_analyzer> read -format db {"/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db"} ! Loading db file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db' ! Warning: Overwriting design file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db'. (DDB-24) ! Current design is now '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder' ! {"fulladder"} ! design_analyzer> create_schematic -size infinite -gen_database 1 ! design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder" ! Current design is 'fulladder'. ! {"fulladder"} ! design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder" ! Current design is 'fulladder'. ! {"fulladder"} ! design_analyzer> create_schematic -size infinite -symbol_view 1 ! design_analyzer> create_schematic -size infinite -hier_view 1 ! design_analyzer> create_schematic -size infinite -schematic_view ! Generating schematic for design: fulladder ! The schematic for design 'fulladder' has 1 page(s). ! 1 ! design_analyzer> \ No newline at end of file --- 156,236 ---- 1 design_analyzer> create_schematic -size infinite -schematic_view -reference ! Generating schematic for design: MUX_RAM_RAM_Width72 ! The schematic for design 'MUX_RAM_RAM_Width72' has 1 page(s). 1 design_analyzer> current_instance ".." ! Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341) ! Current instance is the top-level of design 'Datapath'. "" ! design_analyzer> Information: Building the design 'Min_D' instantiated from design 'MAM_D_DigitalWidth32' with ! the parameters "Width => 32". (HDL-193) ! Error: Tried to use a synchronized value ! in call to '<=' ! called from Min_D_Width32 line 58 in file '/a/ursus/chip004/hansi/FPGA/src/Min_D_rtl.vhd' (HDL-107) ! Error: 'Min_D' was not identified as a synthetic library module ! and could not be successfully elaborated from design library 'WORK'. (LINK-10) ! Warning: Unable to resolve reference 'Min_D_Width32' in 'MAM_D_DigitalWidth32'. (LINK-5) ! Information: Building the design 'Max_D' instantiated from design 'MAM_D_DigitalWidth32' with ! the parameters "Width => 32". (HDL-193) ! Error: Tried to use a synchronized value ! in call to '<=' ! called from Max_D_Width32 line 58 in file '/a/ursus/chip004/hansi/FPGA/src/Max_D_rtl.vhd' (HDL-107) ! Error: 'Max_D' was not identified as a synthetic library module ! and could not be successfully elaborated from design library 'WORK'. (LINK-10) ! Warning: Unable to resolve reference 'Max_D_Width32' in 'MAM_D_DigitalWidth32'. (LINK-5) ! current_instance "i_MAM_D_Dig" ! Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341) ! Current instance is '/Datapath/i_MAM_D_Dig'. ! "/Datapath/i_MAM_D_Dig" ! design_analyzer> create_schematic -size infinite -symbol_view -reference ! Warning: Design 'MAM_D_DigitalWidth32' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341) 1 ! design_analyzer> create_schematic -size infinite -hier_view -reference ! Warning: Design 'MAM_D_DigitalWidth32' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341) 1 ! design_analyzer> create_schematic -size infinite -schematic_view -reference ! Warning: Design 'MAM_D_DigitalWidth32' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341) ! Generating schematic for design: MAM_D_DigitalWidth32 ! The schematic for design 'MAM_D_DigitalWidth32' has 1 page(s). ! 1 ! design_analyzer> current_instance ".." ! Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341) ! Current instance is the top-level of design 'Datapath'. ! "" ! design_analyzer> Information: Building the design 'Min_A' instantiated from design 'MAM_A_AnalogWidth10_AverageWidth36' with ! the parameters "Width => 10". (HDL-193) ! Error: Tried to use a synchronized value ! in call to '<=' ! called from Min_A_Width10 line 55 in file '/a/ursus/chip004/hansi/FPGA/src/Min_A_rtl.vhd' (HDL-107) ! Error: 'Min_A' was not identified as a synthetic library module ! and could not be successfully elaborated from design library 'WORK'. (LINK-10) ! Warning: Unable to resolve reference 'Min_A_Width10' in 'MAM_A_AnalogWidth10_AverageWidth36'. (LINK-5) ! Information: Building the design 'Avg_A' instantiated from design 'MAM_A_AnalogWidth10_AverageWidth36' with ! the parameters "WidthIn => 10, WidthOut => 36". (HDL-193) ! Error: Can't determine type of aggregate or concat ! in routine Avg_A_WidthIn10_WidthOut36 line 57 in file '/a/ursus/chip004/hansi/FPGA/src/Avg_A_rtl.vhd' (HDL-123) ! Error: 'Avg_A' was not identified as a synthetic library module ! and could not be successfully elaborated from design library 'WORK'. (LINK-10) ! Warning: Unable to resolve reference 'Avg_A_WidthIn10_WidthOut36' in 'MAM_A_AnalogWidth10_AverageWidth36'. (LINK-5) ! Information: Building the design 'Max_A' instantiated from design 'MAM_A_AnalogWidth10_AverageWidth36' with ! the parameters "Width => 10". (HDL-193) ! Error: Tried to use a synchronized value ! in call to '<=' ! called from Max_A_Width10 line 55 in file '/a/ursus/chip004/hansi/FPGA/src/Max_A_rtl.vhd' (HDL-107) ! Error: 'Max_A' was not identified as a synthetic library module ! and could not be successfully elaborated from design library 'WORK'. (LINK-10) ! Warning: Unable to resolve reference 'Max_A_Width10' in 'MAM_A_AnalogWidth10_AverageWidth36'. (LINK-5) ! current_instance "i_MAM_A_Ch1" ! Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341) ! Current instance is '/Datapath/i_MAM_A_Ch1'. ! "/Datapath/i_MAM_A_Ch1" ! design_analyzer> create_schematic -size infinite -symbol_view -reference ! Warning: Design 'MAM_A_AnalogWidth10_AverageWidth36' has '3' unresolved references. For more detailed information, use the "link" command. (UID-341) 1 ! design_analyzer> create_schematic -size infinite -hier_view -reference ! Warning: Design 'MAM_A_AnalogWidth10_AverageWidth36' has '3' unresolved references. For more detailed information, use the "link" command. (UID-341) 1 ! design_analyzer> ! Thank you... |
From: Johann G. <han...@us...> - 2003-05-15 07:57:37
|
Update of /cvsroot/dso/FPGA/dc In directory sc8-pr-cvs1:/tmp/cvs-serv14499 Added Files: .synopsys_dc.setup command.log synthesize view_command.log Log Message: --- NEW FILE: .synopsys_dc.setup --- /* set some variables for logfiles */ designer = "VHDL Training Example" company = "Vienna University of Technology" SYNOPSYS = get_unix_variable("SYNOPSYS") /* define search path where to search files during compilation */ search_path = { . , \ /home/mietec/ads98.1/cmos035/v1.8/syn98.2 , \ SYNOPSYS + "/libraries/syn"} link_library = { "*" , MTC45000.db , MTC45000_WL_WORST.db } target_library = { MTC45000.db MTC45000_WL_WORST.db } symbol_library = { MTC45000.sdb} synthetic_library = {standard.sldb} define_design_lib work -path ./lib bus_naming_style = "%s<%d>" bus_dimension_separator_style = "><" bus_inference_style = "%s<%d>" edifout_netlist_only = true edifout_power_and_ground_representation = cell edifout_write_properties_list = {INIT IO LOC PWR_MODE PAD_LOCATION PART} edifout_no_array = true --- NEW FILE: command.log --- /* krypton -- Thu May 15 09:56:17 2003 Initial dc_shell Variable Values */ _bs_arch = "sparcOS5" _bs_suppress_errors = {"PWR-18", "OPT-931", "OPT-932"} _bs_valid_program = "true" acs_area_report_suffix = "area" acs_bs_exec = "" acs_budget_output_file_suffix = "btcl.out" acs_budget_script_file_suffix = "btcl" acs_budgeted_cstr_suffix = "con" acs_compile_script_suffix = "autoscr" acs_constraint_file_suffix = "con" acs_cstr_report_suffix = "cstr" acs_db_suffix = "db" acs_dc_exec = "" acs_global_user_compile_strategy_script = "default.compile" acs_log_file_suffix = "log" acs_makefile_name = "Makefile" acs_num_parallel_jobs = "1" acs_override_script_suffix = "scr" acs_qor_report_suffix = "qor" acs_script_mode = "dcsh" acs_timing_report_suffix = "tim" acs_tr_exec = "" acs_use_lsf = "false" acs_user_budgeting_script = "budget.scr" acs_user_compile_strategy_script_suffix = "compile" acs_work_dir = "/a/ursus/chip004/hansi/FPGA/dc" atpg_bidirect_output_only = "false" atpg_test_asynchronous_pins = "true" auto_link_disable = "false" auto_link_options = "-all" auto_wire_load_selection = "true" bc_allow_shared_memories = "false" bc_chain_read_into_mem = "true" bc_chain_read_into_oper = "true" bc_constrain_signal_memories = "false" bc_detect_array_accesses = "false" bc_detect_memory_accesses = "false" bc_enable_analysis_info = "false" bc_enable_chaining = "true" bc_enable_multi_cycle = "true" bc_enable_speculative_execution = "false" bc_estimate_mux_input = 4 bc_estimate_timing_effort = "high" bc_fsm_coding_style = "one_hot" bc_group_eql_logic = "true" bc_group_index_logic = "true" bc_infer_multibit = "false" bc_minimum_multibit_component_width = 4 bc_report_filter = "" bc_time_all_sequential_op_bindings = "false" bc_use_registerfiles = "false" bin_path = "/home/synopsys/9910/sparcOS5/syn/bin" bus_dimension_separator_style = "><" bus_extraction_style = "%s[%d:%d]" bus_inference_descending_sort = "true" bus_inference_style = "%s<%d>" bus_minus_style = "-%d" bus_multiple_separator_style = "," bus_naming_style = "%s<%d>" bus_range_separator_style = ":" cache_dir_chmod_octal = "777" cache_file_chmod_octal = "666" cache_read = {"/home/synopsys/9910/"} cache_read_info = "false" cache_write = "/home/synopsys/9910/" cache_write_info = "false" change_names_dont_change_bus_members = "false" change_names_update_inst_tree = "true" check_error_list = {"CMD-004", "CMD-006", "CMD-007", "CMD-008", "CMD-009", "CMD-010", "CMD-011", "CMD-012", "CMD-014", "CMD-015", "CMD-016", "CMD-019", "CMD-026", "CMD-031", "CMD-037", "DB-1", "DCSH-11", "DES-001", "FILE-1", "FILE-2", "FILE-3", "FILE-4", "LINK-5", "LINK-7", "LINT-7", "LINT-20", "LNK-023", "OPT-100", "OPT-101", "OPT-102", "OPT-114", "OPT-124", "OPT-127", "OPT-128", "OPT-155", "OPT-157", "OPT-181", "OPT-462", "UI-11", "UI-14", "UI-15", "UI-16", "UI-17", "UI-19", "UI-20", "UI-21", "UI-22", "UI-23", "UI-40", "UI-41", "UID-4", "UID-6", "UID-7", "UID-8", "UID-9", "UID-13", "UID-14", "UID-15", "UID-19", "UID-20", "UID-25", "UID-27", "UID-28", "UID-29", "UID-30", "UID-32", "UID-58", "UID-87", "UID-103", "UID-109", "UID-270", "UID-272", "UID-403", "UID-440", "UID-444", "UIO-2", "UIO-3", "UIO-4", "UIO-25", "UIO-65", "UIO-66", "UIO-75", "UIO-94", "UIO-95", "EQN-6", "EQN-11", "EQN-15", "EQN-16", "EQN-18", "EQN-20"} command_log_file = "./command.log" company = "Vienna University of Technology" compatibility_version = "1999.10" compile_assume_fully_decoded_three_state_busses = "false" compile_automatic_clock_phase_inference = "strict" compile_checkpoint_cpu_interval = 0.000000 compile_checkpoint_filename = "./CHECKPOINT.db" compile_checkpoint_phases = "false" compile_checkpoint_pre_area_filename = "./CHECKPOINT_PRE_AREA.db" compile_checkpoint_pre_delay_filename = "./CHECKPOINT_PRE_DELAY.db" compile_checkpoint_pre_drc1_filename = "./CHECKPOINT_PRE_DRC1.db" compile_checkpoint_pre_drc2_filename = "./CHECKPOINT_PRE_DRC2.db" compile_cpu_limit = 0.000000 compile_create_mux_op_hierarchy = "true" compile_create_wire_load_table = "false" compile_delete_unloaded_sequential_cells = "true" compile_disable_hierarchical_inverter_opt = "false" compile_dont_touch_annotated_cell_during_inplace_opt = "false" compile_dont_use_dedicated_scanout = 1 compile_dw_simple_mode = "false" compile_fix_cell_degradation = "false" compile_implementation_selection = "true" compile_instance_name_prefix = "U" compile_instance_name_suffix = "" compile_log_format = " %elap_time %area %wns %tns %drc %endpoint" compile_mux_no_boundary_optimization = "false" compile_negative_logic_methodology = "false" compile_new_boolean_structure = "false" compile_no_new_cells_at_top_level = "false" compile_preserve_subdesign_interfaces = "false" compile_sequential_area_recovery = "false" compile_simple_mode_block_effort = "none" compile_top_all_paths = "false" compile_update_annotated_delays_during_inplace_opt = "true" compile_use_fast_delay_mode = "true" compile_use_low_timing_effort = "false" context_check_status = "false" create_clock_no_input_delay = "false" current_design = "<<undefined>>" current_instance = "<<undefined>>" db2sge_bit_type = "std_logic" db2sge_bit_vector_type = "std_logic_vector" db2sge_command = "/home/synopsys/9910/sparcOS5/syn/bin/db2sge" db2sge_display_instance_names = "false" db2sge_display_pin_names = "false" db2sge_display_symbol_names = "false" db2sge_one_name = "'1'" db2sge_output_directory = "" db2sge_overwrite = "true" db2sge_scale = 2 db2sge_script = "/home/synopsys/9910/admin/setup/.dc_write_sge" db2sge_target_xp = "false" db2sge_tcf_package_file = "synopsys_tcf.vhd" db2sge_unknown_name = "'X'" db2sge_use_bustaps = "false" db2sge_use_compound_names = "true" db2sge_use_lib_section = "" db2sge_zero_name = "'0'" dc_shell_mode = "default" dc_shell_status = 1 default_input_delay = 30.000000 default_name_rules = "" default_output_delay = 30.000000 default_port_connection_class = "universal" default_schematic_options = "-size infinite" design_library_file = ".synopsys_vss.setup" designer = "VHDL Training Example" dpcm_debuglevel = "0" dpcm_functionscope = "global" dpcm_level = "performance" dpcm_libraries = {} dpcm_rulepath = {} dpcm_rulespath = {} dpcm_slewlimit = "TRUE" dpcm_tablepath = {} dpcm_temperaturescope = "global" dpcm_version = "IEEE-P1481" dpcm_voltagescope = "global" dpcm_wireloadscope = "global" duplicate_ports = "false" echo_include_commands = "true" eco_align_design_verbose = "false" eco_allow_register_type_difference = "false" eco_connect_resource_cell_inputs = "true" eco_correspondence_analysis_verbose = "false" eco_directives_verbose = "false" eco_implement_effort_level = "low" eco_instance_name_prefix = "eco_" eco_recycle_verbose = "true" eco_remap_register_verbose = "false" eco_reuse_verbose = "false" edifin_autoconnect_offpageconnectors = "false" edifin_autoconnect_ports = "false" edifin_dc_script_flag = "" edifin_delete_empty_cells = "true" edifin_delete_ripper_cells = "true" edifin_ground_net_name = "" edifin_ground_net_property_name = "" edifin_ground_net_property_value = "" edifin_ground_port_name = "" edifin_instance_property_name = "" edifin_lib_in_osc_symbol = "" edifin_lib_in_port_symbol = "" edifin_lib_inout_osc_symbol = "" edifin_lib_inout_port_symbol = "" edifin_lib_logic_0_symbol = "" edifin_lib_logic_1_symbol = "" edifin_lib_mentor_netcon_symbol = "" edifin_lib_out_osc_symbol = "" edifin_lib_out_port_symbol = "" edifin_lib_ripper_bits_property = "" edifin_lib_ripper_bus_end = "" edifin_lib_ripper_cell_name = "" edifin_lib_ripper_view_name = "" edifin_lib_route_grid = 1024 edifin_lib_templates = {} edifin_portinstance_disabled_property_name = "" edifin_portinstance_disabled_property_value = "" edifin_portinstance_property_name = "" edifin_power_net_name = "" edifin_power_net_property_name = "" edifin_power_net_property_value = "" edifin_power_port_name = "" edifin_use_identifier_in_rename = "false" edifin_view_identifier_property_name = "" edifout_dc_script_flag = "" edifout_design_name = "Synopsys_edif" edifout_designs_library_name = "DESIGNS" edifout_display_instance_names = "false" edifout_display_net_names = "false" edifout_external = "true" edifout_external_graphic_view_name = "Graphic_representation" edifout_external_netlist_view_name = "Netlist_representation" edifout_external_schematic_view_name = "Schematic_representation" edifout_ground_name = "logic_0" edifout_ground_net_name = "" edifout_ground_net_property_name = "" edifout_ground_net_property_value = "" edifout_ground_pin_name = "logic_0_pin" edifout_ground_port_name = "GND" edifout_instance_property_name = "" edifout_instantiate_ports = "false" edifout_library_graphic_view_name = "Graphic_representation" edifout_library_netlist_view_name = "Netlist_representation" edifout_library_schematic_view_name = "Schematic_representation" edifout_merge_libraries = "false" edifout_multidimension_arrays = "false" edifout_name_oscs_different_from_ports = "false" edifout_name_rippers_same_as_wires = "false" edifout_netlist_only = "true" edifout_no_array = "true" edifout_numerical_array_members = "false" edifout_pin_direction_in_value = "" edifout_pin_direction_inout_value = "" edifout_pin_direction_out_value = "" edifout_pin_direction_property_name = "" edifout_pin_name_property_name = "" edifout_portinstance_disabled_property_name = "" edifout_portinstance_disabled_property_value = "" edifout_portinstance_property_name = "" edifout_power_and_ground_representation = "cell" edifout_power_name = "logic_1" edifout_power_net_name = "" edifout_power_net_property_name = "" edifout_power_net_property_value = "" edifout_power_pin_name = "logic_1_pin" edifout_power_port_name = "VDD" edifout_skip_port_implementations = "false" edifout_target_system = "" edifout_top_level_symbol = "true" edifout_translate_origin = "" edifout_unused_property_value = "" edifout_write_attributes = "false" edifout_write_constraints = "false" edifout_write_properties_list = {"INIT", "IO", "LOC", "PWR_MODE", "PAD_LOCATION", "PART"} enable_instances_in_report_net = "false" enable_page_mode = "true" enable_recovery_removal_arcs = "false" equationout_and_sign = "*" equationout_or_sign = "+" equationout_postfix_negation = "true" errorcode = "NONE" estimate_resource_preference = "fast" exit_delete_filename_log_file = "true" filename_log_file = "filenames.log" find_converts_name_lists = "false" found_arch_apollo = 0 found_x11_vendor_string_apollo = 0 gen_bussing_exact_implicit = "false" gen_cell_pin_name_separator = "/" gen_create_netlist_busses = "true" gen_dont_show_single_bit_busses = "false" gen_match_ripper_wire_widths = "false" gen_max_compound_name_length = 256 gen_max_ports_on_symbol_side = 0 gen_open_name_postfix = "" gen_open_name_prefix = "Open" gen_show_created_busses = "false" gen_show_created_symbols = "false" gen_single_osc_per_name = "false" generic_symbol_library = "generic.sdb" hdl_keep_licenses = "true" hdl_naming_threshold = 20 hdl_preferred_license = "" hdlin_advisor_directory = "." hdlin_auto_save_templates = "FALSE" hdlin_check_no_latch = "FALSE" hdlin_dont_check_param_width = "FALSE" hdlin_dont_infer_mux_for_resource_sharing = "true" hdlin_dont_turbo_instances_with_generics = "true" hdlin_enable_analysis_info = "false" hdlin_enable_analysis_info_for_analyze = "true" hdlin_enable_vpp = "false" hdlin_ff_always_async_set_reset = "TRUE" hdlin_ff_always_sync_set_reset = "FALSE" hdlin_hide_resource_line_numbers = "FALSE" hdlin_infer_multibit = "default_none" hdlin_infer_mux = "default" hdlin_keep_feedback = "FALSE" hdlin_keep_inv_feedback = "TRUE" hdlin_latch_always_async_set_reset = "FALSE" hdlin_merge_nested_conditional_statements = "false" hdlin_mux_oversize_ratio = 100 hdlin_mux_size_limit = 32 hdlin_preserve_vpp_files = "false" hdlin_reg_report_length = 60 hdlin_replace_synthetic = "FALSE" hdlin_report_inferred_modules = "true" hdlin_translate_off_skip_text = "false" hdlin_vhdl93_concat = "true" hdlin_vpp_temporary_directory = "" hdlin_write_gtech_design_directory = "." hdlout_internal_busses = "FALSE" hier_dont_trace_ungroup = 0 hlo_ignore_priorities = "false" hlo_minimize_tree_delay = "true" hlo_resource_allocation = "constraint_driven" hlo_resource_implementation = "use_fastest" hlo_share_common_subexpressions = "true" hlo_share_effort = "low" hlo_transform_constant_multiplication = "false" init_path = "/home/synopsys/9910/auxx/syn" insert_test_design_naming_style = "%s_test_%d" jtag_manufacturer_id = 0 jtag_part_number = 65535 jtag_port_drive_limit = 6 jtag_test_clock_port_naming_style = "jtag_tck%s" jtag_test_data_in_port_naming_style = "jtag_tdi%s" jtag_test_data_out_port_naming_style = "jtag_tdo%s" jtag_test_mode_select_port_naming_style = "jtag_tms%s" jtag_test_reset_port_naming_style = "jtag_trst%s" jtag_version_number = 0 lbo_cells_in_regions = "false" ldd_return_val = "0" ldd_script = "/home/synopsys/9910/auxx/syn/scripts/list_duplicate_designs.dcsh" libgen_max_differences = -1 link_force_case = "check_reference" link_library = {"*", "MTC45000.db", "MTC45000_WL_WORST.db"} lsiin_net_name_prefix = "NET_" lsiout_inverter_cell = "" lsiout_upcase = "true" ltl_drc_use_center_of_mass = "true" ltl_enable_mean_physical_port_location = "false" ltl_lbo_use_all_transforms = "true" ltl_new_critical_net_fixing_delay = "true" ltl_new_critical_net_fixing_drc = "true" mentor_bidirect_value = "INOUT" mentor_do_path = "" mentor_input_output_property_name = "PINTYPE" mentor_input_value = "IN" mentor_logic_one_value = "1SF" mentor_logic_zero_one_property_name = "INIT" mentor_logic_zero_value = "0SF" mentor_output_value = "OUT" mentor_primitive_property_name = "PRIMITIVE" mentor_primitive_property_value = "MODULE" mentor_reference_property_name = "COMP" mentor_search_path = "" mentor_write_symbols = "true" mgi_scratch_directory = "." multi_pass_test_generation = "false" pla_read_create_flip_flop = "false" plot_box = "false" plot_command = "lpr -Plw" plot_orientation = "best_fit" plot_scale_factor = 100 plotter_maxx = 584 plotter_maxy = 764 plotter_minx = 28 plotter_miny = 28 port_complement_naming_style = "%s_BAR" power_gated_clock_logic = "and buf" power_keep_license_after_power_commands = "false" power_preserve_rtl_hier_names = "false" power_reg_size_threshold = 3 power_rtl_saif_file = "power_rtl.saif" power_sdpd_saif_file = "power_sdpd.saif" power_test_enable = "false" power_test_enable_pin = "TEST_MODE" power_test_obs_logic = "false" power_test_obs_logic_depth = 5 read_db_lib_warnings = "FALSE" read_name_mapping_nowarn_libraries = {} read_translate_msff = "TRUE" reoptimize_design_changed_list_file_name = "" sdfin_fall_cell_delay_type = "maximum" sdfin_fall_net_delay_type = "maximum" sdfin_min_fall_cell_delay = 0.000000 sdfin_min_fall_net_delay = 0.000000 sdfin_min_rise_cell_delay = 0.000000 sdfin_min_rise_net_delay = 0.000000 sdfin_rise_cell_delay_type = "maximum" sdfin_rise_net_delay_type = "maximum" sdfin_top_instance_name = "" sdfout_allow_non_positive_constraints = "false" sdfout_min_fall_cell_delay = 0.000000 sdfout_min_fall_net_delay = 0.000000 sdfout_min_rise_cell_delay = 0.000000 sdfout_min_rise_net_delay = 0.000000 sdfout_time_scale = 1.000000 sdfout_top_instance_name = "" sdfout_write_to_output = "false" search_path = {".", "/home/mietec/ads98.1/cmos035/v1.8/syn98.2", "/home/synopsys/9910/libraries/syn"} sh_command_abbrev_mode = "Anywhere" sh_continue_on_error = "true" sh_enable_page_mode = "true" sh_source_uses_search_path = "true" single_group_per_sheet = "false" site_info_file = "/home/synopsys/9910/admin/license/site_info" sort_outputs = "false" suppress_errors = {"PWR-18", "OPT-931", "OPT-932"} symbol_library = {"MTC45000.sdb"} synlib_disable_limited_licenses = "true" synlib_dont_get_license = {} synlib_evaluation_mode = "false" synlib_model_map_effort = "medium" synlib_optimize_non_cache_elements = "true" synlib_prefer_ultra_license = "false" synlib_preferred_library = {} synlib_sequential_module = "default" synlib_wait_for_design_license = {} synopsys = "/home/synopsys/9910" syntax_check_status = "false" synthetic_library = {"standard.sldb"} target_library = {"MTC45000.db", "MTC45000_WL_WORST.db"} tdlout_upcase = "true" template_naming_style = "%s_%p" template_parameter_style = "%s%d" template_separator_style = "_" test_allow_clock_reconvergence = "true" test_bsd_allow_tolerable_violations = "false" test_bsd_control_cell_drive_limit = 0 test_bsd_manufacturer_id = 0 test_bsd_optimize_control_cell = "false" test_bsd_part_number = 0 test_bsd_version_number = 0 test_bsdl_default_suffix_name = "bsdl" test_bsdl_max_line_length = 80 test_capture_clock_skew = "small_skew" test_cc_ir_masked_bits = 0 test_cc_ir_value_of_masked_bits = 0 test_check_port_changes_in_capture = "true" test_clock_port_naming_style = "test_c%s" test_dedicated_subdesign_scan_outs = "true" test_default_bidir_delay = 55.000000 test_default_delay = 5.000000 test_default_min_fault_coverage = 95 test_default_period = 100.000000 test_default_scan_style = "multiplexed_flip_flop" test_default_strobe = 95.000000 test_default_strobe_width = 0.000000 test_design_analyzer_uses_insert_scan = "true" test_disable_find_best_scan_out = "false" test_disconnect_non_functional_so = 1 test_dont_fix_constraint_violations = "false" test_infer_slave_clock_pulse_after_capture = "infer" test_isolate_hier_scan_out = 0 test_mode_port_inverted_naming_style = "test_mode_i%s" test_mode_port_naming_style = "test_mode%s" test_non_scan_clock_port_naming_style = "test_nsc_%s" test_preview_scan_shows_cell_types = "false" test_protocol_add_cycle = "true" test_scan_clock_a_port_naming_style = "test_sca%s" test_scan_clock_b_port_naming_style = "test_scb%s" test_scan_clock_port_naming_style = "test_sc%s" test_scan_enable_inverted_port_naming_style = "test_sei%s" test_scan_enable_port_naming_style = "test_se%s" test_scan_in_port_naming_style = "test_si%s%s" test_scan_link_so_lockup_key = "l" test_scan_link_wire_key = "w" test_scan_out_port_naming_style = "test_so%s%s" test_scan_segment_key = "s" test_scan_true_key = "t" test_stil_multiclock_capture_procedures = "false" test_stil_netlist_format = "db" test_user_defined_instruction_naming_style = "USER%d" test_user_test_data_register_naming_style = "UTDR%d" test_write_four_cycle_stil_protocol = "false" testsim_print_stats_file = "true" text_editor_command = "xterm -fn 8x13 -e vi %s &" text_print_command = "lpr -Plw" timing_self_loops_no_skew = "false" true_delay_prove_false_backtrack_limit = 1000 true_delay_prove_true_backtrack_limit = 1000 uniquify_naming_style = "%s_%d" use_port_name_for_oscs = "true" verbose_messages = "true" verilogout_debug_mode = "false" verilogout_equation = "false" verilogout_higher_designs_first = "FALSE" verilogout_ignore_case = "false" verilogout_include_files = {} verilogout_levelize = "FALSE" verilogout_no_negative_index = "FALSE" verilogout_no_tri = "false" verilogout_show_unconnected_pins = "FALSE" verilogout_single_bit = "false" verilogout_unconnected_prefix = "SYNOPSYS_UNCONNECTED_" vhdllib_architecture = {"UDSM", "FTSM", "FTGS", "VITAL"} vhdllib_glitch_handle = "true" vhdllib_logic_system = "ieee-1164" vhdllib_logical_name = "" vhdllib_negative_constraint = "false" vhdllib_pulse_handle = "use_vhdllib_glitch_handle" vhdllib_tb_compare = 0 vhdllib_tb_x_eq_dontcare = "FALSE" vhdllib_timing_checks = "true" vhdllib_timing_mesg = "true" vhdllib_timing_xgen = "false" vhdlout_architecture_name = "SYN_%a_%u" vhdlout_bit_type = "std_logic" vhdlout_bit_type_resolved = "TRUE" vhdlout_bit_vector_type = "std_logic_vector" vhdlout_conversion_functions = {} vhdlout_debug_mode = "false" vhdlout_dont_create_dummy_nets = "FALSE" vhdlout_dont_write_types = "FALSE" vhdlout_equations = "FALSE" vhdlout_follow_vector_direction = "FALSE" vhdlout_levelize = "FALSE" vhdlout_one_name = "'1'" vhdlout_package_naming_style = "CONV_PACK_%d" vhdlout_preserve_hierarchical_types = "VECTOR" vhdlout_separate_scan_in = "FALSE" vhdlout_single_bit = "USER" vhdlout_synthesis_off = "TRUE" vhdlout_target_simulator = "" vhdlout_three_state_name = "'Z'" vhdlout_three_state_res_func = "" vhdlout_time_scale = 1.000000 vhdlout_top_configuration_arch_name = "A" vhdlout_top_configuration_entity_name = "E" vhdlout_top_configuration_name = "CFG_TB_E" vhdlout_unknown_name = "'X'" vhdlout_upcase = "FALSE" vhdlout_use_packages = {"IEEE.std_logic_1164"} vhdlout_wired_and_res_func = "" vhdlout_wired_or_res_func = "" vhdlout_write_architecture = "TRUE" vhdlout_write_components = "TRUE" vhdlout_write_entity = "TRUE" vhdlout_write_top_configuration = "FALSE" vhdlout_zero_name = "'0'" view_analyze_file_suffix = {"v", "vhd", "vhdl"} view_arch_types = {"apollo", "decmips", "hp700", "mips", "necmips", "rs6000", "sgimips", "sonymips", "sun3", "sparc"} view_background = "black" view_cache_images = "true" view_command_log_file = "./view_command.log" view_command_win_max_lines = 1000 view_dialogs_modal = "true" view_disable_cursor_warping = "true" view_disable_error_windows = "false" view_disable_output = "false" view_error_window_count = 6 view_execute_script_suffix = {".script", ".scr", ".dcs", ".dcv", ".dc", ".con"} view_info_search_cmd = "/home/synopsys/9910/infosearch/scripts/InfoSearch" view_log_file = "" view_on_line_doc_cmd = "/home/synopsys/9910/sold" view_read_file_suffix = {"db", "gdb", "sdb", "edif", "eqn", "fnc", "lsi", "mif", "NET", "pla", "st", "tdl", "v", "vhd", "vhdl", "xnf"} view_script_submenu_items = {"DA to SGE Transfer", "write_sge"} view_tools_menu_items = {} view_use_small_cursor = "" view_use_x_routines = "true" view_write_file_suffix = {"gdb", "db", "sdb", "do", "edif", "eqn", "fnc", "lsi", "NET", "neted", "pla", "st", "tdl", "v", "vhd", "vhdl", "xnf"} write_name_mapping_nowarn_libraries = {} write_name_nets_same_as_ports = "false" write_test_formats = {"synopsys", "tssi_ascii", "tds", "verilog", "vhdl", "wgl"} write_test_include_scan_cell_info = "true" write_test_input_dont_care_value = "X" write_test_max_cycles = 0 write_test_max_scan_patterns = 0 write_test_pattern_set_naming_style = "TC_Syn_%d" write_test_round_timing_values = "true" write_test_scan_check_file_naming_style = "%s_schk.%s" write_test_vector_file_naming_style = "%s_%d.%s" x11_set_cursor_background = "" x11_set_cursor_foreground = "" x11_set_cursor_number = -1 xnfin_dff_clock_enable_pin_name = "CE" xnfin_dff_clock_pin_name = "C" xnfin_dff_data_pin_name = "D" xnfin_dff_q_pin_name = "Q" xnfin_dff_reset_pin_name = "RD" xnfin_dff_set_pin_name = "SD" xnfin_family = "4000" xnfin_ignore_pins = "GTS GSR GR" xnfout_clock_attribute_style = "CLK_ONLY" xnfout_constraints_per_endpoint = "50" xnfout_default_time_constraints = "true" xnfout_library_version = "" xterm_executable = "xterm" /* Initial dc_shell Aliases */ alias analyze_scan "preview_scan" alias check_clocks "check_timing" alias compile_inplace_changed_list_file_name "reoptimize_design_changed_list_file_name" alias compile_test "insert_test" alias create_test_vectors "create_test_patterns" alias disable_timing "set_disable_timing" alias dont_touch "set_dont_touch" alias dont_touch_network "set_dont_touch_network" alias dont_use "set_dont_use" alias est_resource_preference "estimate_resource_preference" alias fix_hold "set_fix_hold" alias free "remove_design" alias fsm_minimize "minimize_fsm" alias fsm_reduce "reduce_fsm" alias gen "create_schematic" alias group_bus "create_bus" alias groupvar "group_variable" alias hist "history" alias lint "check_design" alias list_duplicate_designs "include -quiet ldd_script; dc_shell_status = ldd_return_val " alias ls "sh ls -aC " alias man "help" alias prefer "set_prefer" alias remove_package "echo remove_package command is obsolete: packages are stored on disk not in-memory:" alias report_attributes "report_attribute" alias report_clock_constraint "report_timing -path end -to all_registers(-data_pins)" alias report_clock_tree "report_transitive_fanout -clock_tree" alias report_clocks "report_clock" alias report_constraints "report_constraint" alias report_register "report_timing_requirements;report_clock -skew" alias report_synthetic "report_cell" alias set_connect_delay "set_annotated_delay -net" alias set_internal_arrival "set_arrival" alias set_internal_load "set_load" alias set_ultra_mode "set_ultra_optimization" alias site_info "sh cat site_info_file" alias ungroup_bus "remove_bus" alias verify "compare_design" alias view_cursor_number "x11_set_cursor_number" alias write_sge "include db2sge_script" /* dc_shell Command Log */ /* ----------------------------------------------------- */ /* This is the synthesis script for the fulladder design */ /* ----------------------------------------------------- */ /* write some informative data to the log file */ sh date sh hostname /* main module of our design */ main_module = datapath /* file list of our design, without ".vhd" extension */ file_list = {Avg_A_, \ Avg_A_rtl, \ DEMUX_PP_, \ DEMUX_PP_rtl, \ Datapath_, \ Datapath_struc, \ Join_Avg_, \ Join_Avg_struc, \ Join_MinMax_, \ Join_MinMax_struc, \ Latch_A_, \ Latch_A_rtl, \ Latch_D_, \ Latch_D_rtl, \ MAM_A_, \ MAM_A_P_, \ MAM_A_P_struc, \ MAM_A_struc, \ MAM_D_, \ MAM_D_P_, \ MAM_D_P_struc, \ MAM_D_struc, \ MUX_4_N_, \ MUX_4_N_rtl, \ MUX_AD_, \ MUX_AD_struc, \ MUX_N_1_, \ MUX_N_1_rtl, \ MUX_RAM_, \ MUX_RAM_rtl, \ MUX_uC_, \ MUX_uC_rtl, \ Max_A_, \ Max_A_rtl, \ Max_D_, \ Max_D_rtl, \ Min_A_, \ Min_A_rtl, \ Min_D_, \ Min_D_rtl, \ PP_Clk_, \ PP_Clk_rtl, \ types_p } /* directory structure variables used later in the script */ db_area = "./db/" vhd_area = "../src/" report_area = "./reports/" script_area = "./scr/" /* analyze every VHDL file only for syntax */ foreach (member, file_list) { analyze -format vhdl vhd_area + member + ".vhd" if (dc_shell_status == 0) { echo "ANALYSIS ERROR OR FILE " member " NOT FOUND" quit } } --- NEW FILE: synthesize --- #!/bin/csh dc_shell -f ./scr/synth_dc.scr >& ./log/synth.log & --- NEW FILE: view_command.log --- Design Analyzer (TM) DC Professional (TM) DC Expert (TM) DC Ultra (TM) FPGA Compiler (TM) VHDL Compiler (TM) HDL Compiler (TM) Library Compiler (TM) Power Compiler (TM) Test Compiler (TM) CTV-Interface DesignWare Developer (TM) DesignPower (TM) Version 1999.10 -- Sep 02, 1999 Copyright (c) 1988-1999 by Synopsys, Inc. ALL RIGHTS RESERVED design_analyzer> read -format db {"/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db"} Loading db file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db' Current design is now '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder' {"fulladder", "or_gate", "halfadder"} design_analyzer> create_schematic -size infinite -gen_database Loading db file '/home/synopsys/9910/libraries/syn/generic.sdb' Loading db file '/home/mietec/ads98.1/cmos035/v1.8/syn98.2/MTC45000.sdb' Loading db file '/home/synopsys/9910/libraries/syn/1_25.font' 1 design_analyzer> Loading db file '/home/mietec/ads98.1/cmos035/v1.8/syn98.2/MTC45000.db' Loading db file '/home/mietec/ads98.1/cmos035/v1.8/syn98.2/MTC45000_WL_WORST.db' Loading db file '/home/synopsys/9910/libraries/syn/gtech.db' Loading db file '/home/synopsys/9910/libraries/syn/standard.sldb' create_schematic -size infinite -symbol_view 1 design_analyzer> create_schematic -size infinite -hier_view 1 design_analyzer> create_schematic -size infinite -schematic_view Generating schematic for design: fulladder The schematic for design 'fulladder' has 1 page(s). 1 design_analyzer> current_instance "i_halfadder2" Current instance is '/fulladder/i_halfadder2'. "/fulladder/i_halfadder2" design_analyzer> create_schematic -size infinite -symbol_view -reference 1 design_analyzer> create_schematic -size infinite -hier_view -reference 1 design_analyzer> create_schematic -size infinite -schematic_view -reference Generating schematic for design: halfadder The schematic for design 'halfadder' has 1 page(s). 1 design_analyzer> read -format db {"/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db"} Loading db file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db' Current design is now '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder' {"fulladder"} design_analyzer> create_schematic -size infinite -gen_database 1 design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder" Current design is 'fulladder'. {"fulladder"} design_analyzer> current_instance "i_halfadder2" Current instance is '/fulladder/i_halfadder2'. "/fulladder/i_halfadder2" design_analyzer> read -format db {"/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db"} Loading db file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db' Warning: Overwriting design file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db'. (DDB-24) Current design is now '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder' {"fulladder"} design_analyzer> create_schematic -size infinite -gen_database 1 design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder" Current design is 'fulladder'. {"fulladder"} design_analyzer> current_instance "i_halfadder2" Current instance is '/fulladder/i_halfadder2'. "/fulladder/i_halfadder2" design_analyzer> current_instance ".." Current instance is the top-level of design 'fulladder'. "" design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder" Current design is 'fulladder'. {"fulladder"} design_analyzer> reset_design Resetting current design 'fulladder' 1 design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder" Current design is 'fulladder'. {"fulladder"} design_analyzer> reset_design Resetting current design 'fulladder' 1 design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:halfadder" Current design is 'halfadder'. {"halfadder"} design_analyzer> reset_design Resetting current design 'halfadder' 1 design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:or_gate" Current design is 'or_gate'. {"or_gate"} design_analyzer> reset_design Resetting current design 'or_gate' 1 design_analyzer> read -format db {"/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db"} Loading db file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db' Warning: Overwriting design file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db'. (DDB-24) Current design is now '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder' {"fulladder"} design_analyzer> create_schematic -size infinite -gen_database 1 design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder" Current design is 'fulladder'. {"fulladder"} design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder" Current design is 'fulladder'. {"fulladder"} design_analyzer> create_schematic -size infinite -symbol_view 1 design_analyzer> create_schematic -size infinite -hier_view 1 design_analyzer> create_schematic -size infinite -schematic_view Generating schematic for design: fulladder The schematic for design 'fulladder' has 1 page(s). 1 design_analyzer> |
From: Johann G. <han...@us...> - 2003-05-15 07:51:38
|
Update of /cvsroot/dso/FPGA/dc/scr In directory sc8-pr-cvs1:/tmp/cvs-serv12565/dc/scr Log Message: Directory /cvsroot/dso/FPGA/dc/scr added to the repository |
From: Johann G. <han...@us...> - 2003-05-15 07:51:38
|
Update of /cvsroot/dso/FPGA/dc/reports In directory sc8-pr-cvs1:/tmp/cvs-serv12565/dc/reports Log Message: Directory /cvsroot/dso/FPGA/dc/reports added to the repository |
From: Johann G. <han...@us...> - 2003-05-15 07:51:37
|
Update of /cvsroot/dso/FPGA/dc/log In directory sc8-pr-cvs1:/tmp/cvs-serv12565/dc/log Log Message: Directory /cvsroot/dso/FPGA/dc/log added to the repository |
From: Johann G. <han...@us...> - 2003-05-15 07:51:37
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Update of /cvsroot/dso/FPGA/dc/lib In directory sc8-pr-cvs1:/tmp/cvs-serv12565/dc/lib Log Message: Directory /cvsroot/dso/FPGA/dc/lib added to the repository |
From: Johann G. <han...@us...> - 2003-05-15 07:51:36
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Update of /cvsroot/dso/FPGA/dc/db In directory sc8-pr-cvs1:/tmp/cvs-serv12565/dc/db Log Message: Directory /cvsroot/dso/FPGA/dc/db added to the repository |
From: Johann G. <han...@us...> - 2003-05-15 07:51:35
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Update of /cvsroot/dso/FPGA/dc In directory sc8-pr-cvs1:/tmp/cvs-serv12565/dc Log Message: Directory /cvsroot/dso/FPGA/dc added to the repository |
From: Johann G. <han...@us...> - 2003-05-14 10:06:56
|
Update of /cvsroot/dso/FPGA In directory sc8-pr-cvs1:/tmp/cvs-serv28606 Modified Files: TODO Log Message: updated TODO Index: TODO =================================================================== RCS file: /cvsroot/dso/FPGA/TODO,v retrieving revision 1.7 retrieving revision 1.8 diff -C2 -d -r1.7 -r1.8 *** TODO 14 May 2003 08:37:57 -0000 1.7 --- TODO 14 May 2003 10:06:52 -0000 1.8 *************** *** 20,21 **** --- 20,22 ---- Trigger, MAM_D, MAM_D_P, Join_MinMax, Join_Avg - make drawings for the RTL architectures: (use from Synplify or so) + - update drawing for DEMUX_PP and Datapath with the new MAM_PP_i signal |
From: Johann G. <han...@us...> - 2003-05-14 08:38:04
|
Update of /cvsroot/dso/FPGA/tb In directory sc8-pr-cvs1:/tmp/cvs-serv26131/tb Modified Files: tb_Datapath.vhd Log Message: added "-93" to _all_ "vcom" commands in msim/compile.tcl updated TODO corrected DEMUX_PP to use the "MAM_i" input which determines wether the data from RAM was MAM'ed or not. Corrected Datapath and testbench to reflect these changes. Moved type "Test_t" from types_p.vhd to tb_Datapath.vhd. Index: tb_Datapath.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/tb/tb_Datapath.vhd,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** tb_Datapath.vhd 8 May 2003 14:48:39 -0000 1.6 --- tb_Datapath.vhd 14 May 2003 08:38:00 -0000 1.7 *************** *** 29,32 **** --- 29,34 ---- ------------------------------------------------------------------------------- + -- run for >2700ns + library IEEE; use IEEE.std_logic_1164.all; *************** *** 63,66 **** --- 65,69 ---- signal Latch : std_logic := '0'; -- latches hold values signal MAAM : MAAM_t; -- select Min/Avg1/Avg2/Max to be written to RAM or directed to MUX_uC + signal MAM_PP : std_logic := '1'; -- tell DEMUX_PP wether data from RAM was MAM'ed or not signal RAMdir : std_logic := '0'; -- read/write RAM signal EnPP : std_logic := '0'; -- enable PP_Clk *************** *** 70,73 **** --- 73,78 ---- signal uC : std_logic_vector(7 downto 0); -- output to uC + type Test_t is (IdlePrep,Test1,Test2,Test3,Test4,Test5,Test6); -- for tb_Datapath + -- signals especially for testing signal t_RAM : std_logic_vector(71 downto 0) :=(others => 'Z'); -- varify RAM signal *************** *** 100,107 **** Latch_AD_i : in std_logic; -- activate Latches at input side MAAM_AD_i : in MAAM_t; -- select which group to be routed to RAM ! Through_PP_i : in std_logic; -- activate "Through_i" on MAMs at output side En_PP_i : in std_logic; -- enable PP_Clk unit MAAM_PP_i : in MAAM_t; -- select which group to be routet to the µC uC_Select_i : in std_logic_vector( 3 downto 0); -- select 8-bit packet from 72-bit data bus --- 105,113 ---- Latch_AD_i : in std_logic; -- activate Latches at input side MAAM_AD_i : in MAAM_t; -- select which group to be routed to RAM ! Through_PP_i : in std_logic; -- activate "Through_i" on MAMs at output side En_PP_i : in std_logic; -- enable PP_Clk unit MAAM_PP_i : in MAAM_t; -- select which group to be routet to the µC + MAM_PP_i : in std_logic; -- tell DEMUX_PP if data from RAM was MAM'ed or not uC_Select_i : in std_logic_vector( 3 downto 0); -- select 8-bit packet from 72-bit data bus *************** *** 130,137 **** Through_AD_i => ThAD, Latch_AD_i => Latch, ! MAAM_AD_i => MAAM , En_PP_i => EnPP, Through_PP_i => ThPP, ! MAAM_PP_i => MAAM , uC_Select_i => uCsel, RAM_Dir_i => RAMdir); --- 136,144 ---- Through_AD_i => ThAD, Latch_AD_i => Latch, ! MAAM_AD_i => MAAM, En_PP_i => EnPP, Through_PP_i => ThPP, ! MAAM_PP_i => MAAM, ! MAM_PP_i => MAM_PP, uC_Select_i => uCsel, RAM_Dir_i => RAMdir); *************** *** 366,370 **** -- test not possible: DEMUX_PP does not allow this configuration! ! end process p_Test; --- 373,380 ---- -- test not possible: DEMUX_PP does not allow this configuration! ! ! -- TODO: write this test, it is now possible with the signal "MAM_PP" ! ! assert false report "Ready" severity FAILURE; end process p_Test; |
From: Johann G. <han...@us...> - 2003-05-14 08:38:04
|
Update of /cvsroot/dso/FPGA/src In directory sc8-pr-cvs1:/tmp/cvs-serv26131/src Modified Files: DEMUX_PP_.vhd DEMUX_PP_rtl.vhd Datapath_.vhd Datapath_struc.vhd types_p.vhd Log Message: added "-93" to _all_ "vcom" commands in msim/compile.tcl updated TODO corrected DEMUX_PP to use the "MAM_i" input which determines wether the data from RAM was MAM'ed or not. Corrected Datapath and testbench to reflect these changes. Moved type "Test_t" from types_p.vhd to tb_Datapath.vhd. Index: DEMUX_PP_.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/src/DEMUX_PP_.vhd,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** DEMUX_PP_.vhd 27 Feb 2003 10:16:02 -0000 1.3 --- DEMUX_PP_.vhd 14 May 2003 08:37:59 -0000 1.4 *************** *** 60,65 **** Max4_o : out std_logic_vector(AnalogWidth-1 downto 0); -- output of maximum of 4th channel MinD_o : out std_logic_vector(DigitalWidth-1 downto 0); -- output of minimum of digital channels ! MaxD_o : out std_logic_vector(DigitalWidth-1 downto 0) -- output of maximum of digital channels ! -- MAM_i : in std_logic); -- tell the Demux ! ); -- if the data from RAM has been MAM'ed or not end DEMUX_PP; --- 60,65 ---- Max4_o : out std_logic_vector(AnalogWidth-1 downto 0); -- output of maximum of 4th channel MinD_o : out std_logic_vector(DigitalWidth-1 downto 0); -- output of minimum of digital channels ! MaxD_o : out std_logic_vector(DigitalWidth-1 downto 0); -- output of maximum of digital channels ! MAM_i : in std_logic -- tell the Demux ! ); -- if the data from RAM has been MAM'ed or not end DEMUX_PP; Index: DEMUX_PP_rtl.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/src/DEMUX_PP_rtl.vhd,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** DEMUX_PP_rtl.vhd 26 Feb 2003 16:37:42 -0000 1.4 --- DEMUX_PP_rtl.vhd 14 May 2003 08:38:00 -0000 1.5 *************** *** 50,95 **** MinD_o <= RAM_i(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth);-- when MAM_I = '0' else (others => '0'); MaxD_o <= RAM_i(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth);-- when MAM_I = '0' else (others => '0'); - Avg1_o <= RAM_i( AverageWidth-1 downto 0);-- when MAM_I = '1' else (others => '0'); - Avg2_o <= RAM_i( 2*AverageWidth-1 downto AverageWidth);-- when MAM_I = '1' else (others => '0'); - Avg3_o <= RAM_i( AverageWidth-1 downto 0);-- when MAM_I = '1' else (others => '0'); - Avg4_o <= RAM_i( 2*AverageWidth-1 downto AverageWidth);-- when MAM_I = '1' else (others => '0'); - - -- Attention: The implementation with the following process synthesizes - -- latches for each output!!! Use the above concurrent implementation to avoid - -- this. XSE simply uses AND gates for this. Hehe. ! -- Remark II: stupidly I thought this Demux needs to know if the incoming ! -- signals via RAM_i are either a Min/Max/Direct or a Avg1/Avg2 constellation. ! -- This is not important, because the MAM_A_P and MAM_D_P connected with it ! -- have their own ClkMin/ClkAvg1/... So they only take the signals they need. ! -- Distributing wrong signals (i.e. because of assuming a wrong input ! -- constellation) is no problem. No ClkXxx is generated. - -- -- purpose: demultiplex data from RAM word to Min/Avg/Max of all channels - -- -- type : combinational - -- -- inputs : MAM_i,RAM_i - -- -- outputs: Min[1234D]_o,Avg[1234]_o,Max[1234D]_o - -- DEMUX: process (MAM_i,RAM_i) - -- begin -- process DEMUX - -- case MAM_i is - -- when '0' => Min1_o <= RAM_i( AnalogWidth-1 downto 0); - -- Max1_o <= RAM_i( AnalogWidth-1 downto 0); - -- Min2_o <= RAM_i(2*AnalogWidth-1 downto AnalogWidth); - -- Max2_o <= RAM_i(2*AnalogWidth-1 downto AnalogWidth); - -- Min3_o <= RAM_i(3*AnalogWidth-1 downto 2*AnalogWidth); - -- Max3_o <= RAM_i(3*AnalogWidth-1 downto 2*AnalogWidth); - -- Min4_o <= RAM_i(4*AnalogWidth-1 downto 3*AnalogWidth); - -- Max4_o <= RAM_i(4*AnalogWidth-1 downto 3*AnalogWidth); - -- MinD_o <= RAM_i(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth); - -- MaxD_o <= RAM_i(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth); - -- when '1' => Avg1_o <= RAM_i( AverageWidth-1 downto 0); - -- Avg2_o <= RAM_i(2*AverageWidth-1 downto AverageWidth); - -- Avg3_o <= RAM_i( AverageWidth-1 downto 0); - -- Avg4_o <= RAM_i(2*AverageWidth-1 downto AverageWidth); - -- when others => null; - -- end case; - - -- end process DEMUX; - - end rtl; --- 50,76 ---- MinD_o <= RAM_i(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth);-- when MAM_I = '0' else (others => '0'); MaxD_o <= RAM_i(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth);-- when MAM_I = '0' else (others => '0'); ! -- purpose: demultiplex data from RAM word to Avg of all channels ! -- type : combinational ! -- inputs : MAM_i,RAM_i ! -- outputs: Avg[1234]_o ! DEMUX: process (MAM_i,RAM_i) ! begin -- process DEMUX ! case MAM_i is ! when '0' => Avg1_o(AnalogWidth -1 downto 0) <= RAM_i( AnalogWidth-1 downto 0); ! Avg2_o(AnalogWidth -1 downto 0) <= RAM_i(2*AnalogWidth-1 downto AnalogWidth); ! Avg3_o(AnalogWidth -1 downto 0) <= RAM_i(3*AnalogWidth-1 downto 2*AnalogWidth); ! Avg4_o(AnalogWidth -1 downto 0) <= RAM_i(4*AnalogWidth-1 downto 3*AnalogWidth); ! Avg1_o(AverageWidth-1 downto AnalogWidth) <= (others => '0'); ! Avg2_o(AverageWidth-1 downto AnalogWidth) <= (others => '0'); ! Avg3_o(AverageWidth-1 downto AnalogWidth) <= (others => '0'); ! Avg4_o(AverageWidth-1 downto AnalogWidth) <= (others => '0'); ! when others => Avg1_o <= RAM_i( AverageWidth-1 downto 0); ! Avg2_o <= RAM_i(2*AverageWidth-1 downto AverageWidth); ! Avg3_o <= RAM_i( AverageWidth-1 downto 0); ! Avg4_o <= RAM_i(2*AverageWidth-1 downto AverageWidth); ! end case; ! ! end process DEMUX; end rtl; Index: Datapath_.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/src/Datapath_.vhd,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** Datapath_.vhd 9 Apr 2003 11:10:48 -0000 1.2 --- Datapath_.vhd 14 May 2003 08:38:00 -0000 1.3 *************** *** 62,65 **** --- 62,66 ---- Through_PP_i : in std_logic; -- activate "Through_i" on MAMs at output side En_PP_i : in std_logic; -- enable PP_Clk unit + MAM_PP_i : in std_logic; -- tell DEMUX_PP if data from RAM was MAM'ed or not MAAM_PP_i : in MAAM_t; -- select which group to be routet to the µC uC_Select_i : in std_logic_vector( 3 downto 0); -- select 8-bit packet from 72-bit data bus Index: Datapath_struc.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/src/Datapath_struc.vhd,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** Datapath_struc.vhd 15 Apr 2003 13:00:51 -0000 1.3 --- Datapath_struc.vhd 14 May 2003 08:38:00 -0000 1.4 *************** *** 146,152 **** Max4_o : out std_logic_vector(AnalogWidth -1 downto 0); -- output of maximum of 4th channel MinD_o : out std_logic_vector(DigitalWidth-1 downto 0); -- output of minimum of digital channels ! MaxD_o : out std_logic_vector(DigitalWidth-1 downto 0) -- output of maximum of digital channels ! -- MAM_i : in std_logic); -- tell the Demux ! ); -- if the data from RAM has been MAM'ed or not end component; --- 146,152 ---- Max4_o : out std_logic_vector(AnalogWidth -1 downto 0); -- output of maximum of 4th channel MinD_o : out std_logic_vector(DigitalWidth-1 downto 0); -- output of minimum of digital channels ! MaxD_o : out std_logic_vector(DigitalWidth-1 downto 0); -- output of maximum of digital channels ! MAM_i : in std_logic -- tell the Demux ! ); -- if the data from RAM has been MAM'ed or not end component; *************** *** 459,463 **** MinD_o => Min_D_Dig, MaxD_o => Max_D_Dig, ! RAM_i => RAM_PP); i_MAM_A_P_Ch1 : MAM_A_P --- 459,464 ---- MinD_o => Min_D_Dig, MaxD_o => Max_D_Dig, ! RAM_i => RAM_PP, ! MAM_i => MAM_PP_i); i_MAM_A_P_Ch1 : MAM_A_P Index: types_p.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/src/types_p.vhd,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** types_p.vhd 8 May 2003 14:48:39 -0000 1.3 --- types_p.vhd 14 May 2003 08:38:00 -0000 1.4 *************** *** 32,36 **** type MAAM_t is (MAAM_Min,MAAM_Avg1,MAAM_Avg2,MAAM_Max); -- MUX selection which data group for the RAM - type Test_t is (IdlePrep,Test1,Test2,Test3,Test4,Test5,Test6); -- for tb_Datapath end types_p; --- 32,35 ---- |
From: Johann G. <han...@us...> - 2003-05-14 08:38:03
|
Update of /cvsroot/dso/FPGA In directory sc8-pr-cvs1:/tmp/cvs-serv26131 Modified Files: TODO Log Message: added "-93" to _all_ "vcom" commands in msim/compile.tcl updated TODO corrected DEMUX_PP to use the "MAM_i" input which determines wether the data from RAM was MAM'ed or not. Corrected Datapath and testbench to reflect these changes. Moved type "Test_t" from types_p.vhd to tb_Datapath.vhd. Index: TODO =================================================================== RCS file: /cvsroot/dso/FPGA/TODO,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** TODO 9 Apr 2003 11:43:54 -0000 1.6 --- TODO 14 May 2003 08:37:57 -0000 1.7 *************** *** 1,5 **** - Architectures for DSO, Control, Kernel and Trigger ! - Testbench for Datapath - tb_MAM_A.vhd: line 84: "1=1" -- can be written as "(true)" - tb_Avg_A.vhd: clock and reset are modelled awkwardly --- 1,7 ---- - Architectures for DSO, Control, Kernel and Trigger ! - Datapath: DEMUX_PP must have an input to select which signals to put to ! the Avg outputs, either if they come from a stored "Avg1:Avg2"/"Avg3:Avg4" ! or they come from a stored "Val1:Val2:Val3:Val4:Dig" - tb_MAM_A.vhd: line 84: "1=1" -- can be written as "(true)" - tb_Avg_A.vhd: clock and reset are modelled awkwardly |
From: Johann G. <han...@us...> - 2003-05-14 08:38:03
|
Update of /cvsroot/dso/FPGA/msim In directory sc8-pr-cvs1:/tmp/cvs-serv26131/msim Modified Files: compile.tcl Log Message: added "-93" to _all_ "vcom" commands in msim/compile.tcl updated TODO corrected DEMUX_PP to use the "MAM_i" input which determines wether the data from RAM was MAM'ed or not. Corrected Datapath and testbench to reflect these changes. Moved type "Test_t" from types_p.vhd to tb_Datapath.vhd. Index: compile.tcl =================================================================== RCS file: /cvsroot/dso/FPGA/msim/compile.tcl,v retrieving revision 1.15 retrieving revision 1.16 diff -C2 -d -r1.15 -r1.16 *** compile.tcl 30 Apr 2003 11:26:27 -0000 1.15 --- compile.tcl 14 May 2003 08:37:59 -0000 1.16 *************** *** 10,72 **** # compile packages ! vcom -work work ../src/types_p.vhd # compile entities ! vcom -work work ../src/Avg_A_.vhd ! vcom -work work ../src/DEMUX_PP_.vhd ! vcom -work work ../src/Join_Avg_.vhd ! vcom -work work ../src/Join_MinMax_.vhd ! vcom -work work ../src/Latch_A_.vhd ! vcom -work work ../src/Latch_D_.vhd ! vcom -work work ../src/MAM_A_.vhd ! vcom -work work ../src/MAM_A_P_.vhd ! vcom -work work ../src/MAM_D_.vhd ! vcom -work work ../src/MAM_D_P_.vhd ! vcom -work work ../src/MUX_4_N_.vhd ! vcom -work work ../src/MUX_AD_.vhd ! vcom -work work ../src/Datapath_.vhd ! vcom -work work ../src/MUX_RAM_.vhd ! vcom -work work ../src/MUX_uC_.vhd ! vcom -work work ../src/Max_A_.vhd ! vcom -work work ../src/Min_A_.vhd ! vcom -work work ../src/Max_D_.vhd ! vcom -work work ../src/Min_D_.vhd ! vcom -work work ../src/PP_Clk_.vhd # compile architectures ! vcom -work work ../src/Avg_A_rtl.vhd ! vcom -work work ../src/DEMUX_PP_rtl.vhd ! vcom -work work ../src/Join_Avg_struc.vhd ! vcom -work work ../src/Join_MinMax_struc.vhd ! vcom -work work ../src/Latch_A_rtl.vhd ! vcom -work work ../src/Latch_D_rtl.vhd ! vcom -work work ../src/MAM_A_P_struc.vhd ! vcom -work work ../src/MAM_A_struc.vhd ! vcom -work work ../src/MAM_D_struc.vhd ! vcom -work work ../src/MAM_D_P_struc.vhd ! vcom -work work ../src/MUX_4_N_rtl.vhd vcom -93 -work work ../src/MUX_AD_struc.vhd ! vcom -work work ../src/MUX_RAM_rtl.vhd ! vcom -work work ../src/MUX_uC_rtl.vhd ! vcom -work work ../src/Min_A_rtl.vhd ! vcom -work work ../src/Max_A_rtl.vhd ! vcom -work work ../src/Latch_A_rtl.vhd ! vcom -work work ../src/Latch_D_rtl.vhd ! vcom -work work ../src/Min_D_rtl.vhd ! vcom -work work ../src/Max_D_rtl.vhd ! vcom -work work ../src/PP_Clk_rtl.vhd vcom -93 -work work ../src/Datapath_struc.vhd # compile testbenches ! vcom -work work ../tb/tb_Join_MinMax.vhd ! vcom -work work ../tb/tb_Min_A.vhd ! vcom -work work ../tb/tb_Max_A.vhd ! vcom -work work ../tb/tb_Join_Avg.vhd ! vcom -work work ../tb/tb_MUX_4_N.vhd ! vcom -work work ../tb/tb_Latch_A.vhd ! vcom -work work ../tb/tb_DEMUX_PP.vhd ! vcom -work work ../tb/tb_Avg_A.vhd ! vcom -work work ../tb/tb_MUX_RAM.vhd ! vcom -work work ../tb/tb_MUX_AD.vhd ! vcom -work work ../tb/tb_MAM_A.vhd ! vcom -work work ../tb/tb_Datapath.vhd \ No newline at end of file --- 10,72 ---- # compile packages ! vcom -93 -work work ../src/types_p.vhd # compile entities ! vcom -93 -work work ../src/Avg_A_.vhd ! vcom -93 -work work ../src/DEMUX_PP_.vhd ! vcom -93 -work work ../src/Join_Avg_.vhd ! vcom -93 -work work ../src/Join_MinMax_.vhd ! vcom -93 -work work ../src/Latch_A_.vhd ! vcom -93 -work work ../src/Latch_D_.vhd ! vcom -93 -work work ../src/MAM_A_.vhd ! vcom -93 -work work ../src/MAM_A_P_.vhd ! vcom -93 -work work ../src/MAM_D_.vhd ! vcom -93 -work work ../src/MAM_D_P_.vhd ! vcom -93 -work work ../src/MUX_4_N_.vhd ! vcom -93 -work work ../src/MUX_AD_.vhd ! vcom -93 -work work ../src/Datapath_.vhd ! vcom -93 -work work ../src/MUX_RAM_.vhd ! vcom -93 -work work ../src/MUX_uC_.vhd ! vcom -93 -work work ../src/Max_A_.vhd ! vcom -93 -work work ../src/Min_A_.vhd ! vcom -93 -work work ../src/Max_D_.vhd ! vcom -93 -work work ../src/Min_D_.vhd ! vcom -93 -work work ../src/PP_Clk_.vhd # compile architectures ! vcom -93 -work work ../src/Avg_A_rtl.vhd ! vcom -93 -work work ../src/DEMUX_PP_rtl.vhd ! vcom -93 -work work ../src/Join_Avg_struc.vhd ! vcom -93 -work work ../src/Join_MinMax_struc.vhd ! vcom -93 -work work ../src/Latch_A_rtl.vhd ! vcom -93 -work work ../src/Latch_D_rtl.vhd ! vcom -93 -work work ../src/MAM_A_P_struc.vhd ! vcom -93 -work work ../src/MAM_A_struc.vhd ! vcom -93 -work work ../src/MAM_D_struc.vhd ! vcom -93 -work work ../src/MAM_D_P_struc.vhd ! vcom -93 -work work ../src/MUX_4_N_rtl.vhd vcom -93 -work work ../src/MUX_AD_struc.vhd ! vcom -93 -work work ../src/MUX_RAM_rtl.vhd ! vcom -93 -work work ../src/MUX_uC_rtl.vhd ! vcom -93 -work work ../src/Min_A_rtl.vhd ! vcom -93 -work work ../src/Max_A_rtl.vhd ! vcom -93 -work work ../src/Latch_A_rtl.vhd ! vcom -93 -work work ../src/Latch_D_rtl.vhd ! vcom -93 -work work ../src/Min_D_rtl.vhd ! vcom -93 -work work ../src/Max_D_rtl.vhd ! vcom -93 -work work ../src/PP_Clk_rtl.vhd vcom -93 -work work ../src/Datapath_struc.vhd # compile testbenches ! vcom -93 -work work ../tb/tb_Join_MinMax.vhd ! vcom -93 -work work ../tb/tb_Min_A.vhd ! vcom -93 -work work ../tb/tb_Max_A.vhd ! vcom -93 -work work ../tb/tb_Join_Avg.vhd ! vcom -93 -work work ../tb/tb_MUX_4_N.vhd ! vcom -93 -work work ../tb/tb_Latch_A.vhd ! vcom -93 -work work ../tb/tb_DEMUX_PP.vhd ! vcom -93 -work work ../tb/tb_Avg_A.vhd ! vcom -93 -work work ../tb/tb_MUX_RAM.vhd ! vcom -93 -work work ../tb/tb_MUX_AD.vhd ! vcom -93 -work work ../tb/tb_MAM_A.vhd ! vcom -93 -work work ../tb/tb_Datapath.vhd \ No newline at end of file |
From: Gerald Z. <ri...@us...> - 2003-05-08 14:48:43
|
Update of /cvsroot/dso/FPGA/tb In directory sc8-pr-cvs1:/tmp/cvs-serv4048/FPGA/tb Modified Files: tb_Datapath.vhd Log Message: first 5 tests running, rest not possible: DEMUX_PP must bei modified; Index: tb_Datapath.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/tb/tb_Datapath.vhd,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** tb_Datapath.vhd 30 Apr 2003 11:26:27 -0000 1.5 --- tb_Datapath.vhd 8 May 2003 14:48:39 -0000 1.6 *************** *** 1,358 **** ! ------------------------------------------------------------------------------- ! -- ! -- Author: Gerald Zach ! -- ! -- Filename: tb_CountDown.vhd ! -- ! -- Date of Creation: 09-04-2003 ! -- ! -- Description: Testbench for Datapath ! -- ! ------------------------------------------------------------------------------- ! -- ! -- Copyright (C) 2003 Gerald Zach ! -- ! -- This program is free software; you can redistribute it and/or modify ! -- it under the terms of the GNU General Public License as published by ! -- the Free Software Foundation; either version 2 of the License, or ! -- (at your option) any later version. ! -- ! -- This program is distributed in the hope that it will be useful, ! -- but WITHOUT ANY WARRANTY; without even the implied warranty of ! -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! -- GNU General Public License for more details. ! -- ! -- You should have received a copy of the GNU General Public License ! -- along with this program; if not, write to the Free Software ! -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ! -- ! ------------------------------------------------------------------------------- ! ! library IEEE; ! use IEEE.std_logic_1164.all; ! use IEEE.std_logic_arith.all; ! use IEEE.std_logic_signed."+"; ! use IEEE.std_logic_signed.">"; ! use IEEE.std_logic_signed."<"; ! use IEEE.std_logic_unsigned.conv_integer; ! use IEEE.math_real.all; ! use work.all; ! ! library work; ! use work.types_p.all; ! ! ! entity tb_Datapath is ! generic ( ! AnalogWidth : integer := 10; -- width of analog inputs ! DigitalWidth : integer := 32; -- width of digital inputs ! RAM_Width : integer := 72; -- width of data bus to RAM ! AverageWidth : integer := 36); -- width of averaged input (actually it is a sum) ! end tb_Datapath; ! ! architecture sim of tb_Datapath is ! signal Clk : std_logic := '0'; -- clock for all components ! signal Reset : std_logic := '1'; -- reset for all components LOW ACTIVE!!! ! signal I1 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel1 input ! signal I2 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel2 input ! signal I3 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel3 input ! signal I4 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel4 input ! signal Di : std_logic_vector(DigitalWidth-1 downto 0) := (others => '0'); -- digital inputs ! signal EnAD : std_logic := '0'; -- enable MAM-units at input ! signal ThAD : std_logic := '0'; -- allow inputs to pass MAM input units ! signal Latch : std_logic := '0'; -- latches hold values ! signal MAAM : MAAM_t; -- select Min/Avg1/Avg2/Max to be written to RAM or directed to MUX_uC ! signal RAMdir : std_logic := '0'; -- read/write RAM ! signal EnPP : std_logic := '0'; -- enable PP_Clk ! signal ThPP : std_logic := '0'; -- pass PP-units ! signal uCsel : std_logic_vector(3 downto 0) := (others => '0'); -- select 8 bit words -> output ! signal RAM : std_logic_vector(RAM_Width-1 downto 0); -- RAM values ! signal uC : std_logic_vector(7 downto 0); -- output to uC ! ! signal t_RAM : std_logic_vector(71 downto 0) :=(others => 'Z'); -- varify RAM signal ! signal t_uC : std_logic_vector(7 downto 0); -- varify uC signal ! signal cs : integer := 0; -- for testing routine ! ! constant T2_clk : time := 6.26 ns; -- half period (80MHz) ! ! component Datapath ! generic ( ! AnalogWidth : integer; -- width of analog inputs ! DigitalWidth : integer; -- width of digital inputs ! RAM_Width : integer); -- width of data bus to RAM ! port ( ! CH1_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 1 ! CH2_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 2 ! CH3_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 3 ! CH4_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 4 ! Dig_i : in std_logic_vector(DigitalWidth-1 downto 0); -- digital input channels ! ! RAM_b : inout std_logic_vector(RAM_Width -1 downto 0); -- data path to memory ! ! uC_o : out std_logic_vector(7 downto 0); -- data bus to µC ! ! Clk : in std_logic; -- clock input ! Reset : in std_logic; -- reset input ! ! En_AD_i : in std_logic; -- enable MAMs at input side ! Through_AD_i : in std_logic; -- activate "Through_i" on MAMs at input side ! Latch_AD_i : in std_logic; -- activate Latches at input side ! MAAM_AD_i : in MAAM_t; -- select which group to be routed to RAM ! ! Through_PP_i : in std_logic; -- activate "Through_i" on MAMs at output side ! En_PP_i : in std_logic; -- enable PP_Clk unit ! MAAM_PP_i : in MAAM_t; -- select which group to be routet to the µC ! uC_Select_i : in std_logic_vector( 3 downto 0); -- select 8-bit packet from 72-bit data bus ! ! RAM_Dir_i : in std_logic); -- direction of RAM access (read/write) ! ! --constant AverageWidth : integer: = AverageWidth ; -- width of averaged input (actually it is a sum) ! end component; ! ! begin -- sim ! ! i_Datapath: Datapath ! generic map ( ! AnalogWidth => AnalogWidth, ! DigitalWidth => DigitalWidth, ! RAM_Width => RAM_Width) ! port map ( ! CH1_i => I1, ! CH2_i => I2, ! CH3_i => I3, ! CH4_i => I4, ! Dig_i => Di, ! RAM_b => RAM, ! uC_o => uC, ! Clk => Clk, ! Reset => Reset, ! En_AD_i => EnAD, ! Through_AD_i => ThAD, ! Latch_AD_i => Latch, ! MAAM_AD_i => MAAM , ! En_PP_i => EnPP, ! Through_PP_i => ThPP, ! MAAM_PP_i => MAAM , ! uC_Select_i => uCsel, ! RAM_Dir_i => RAMdir); ! ! -- purpose: generate Clk signal ! -- type : combinational ! -- inputs : ! -- outputs: Clk ! p_Clk: process ! begin -- process p_Clk ! Clk <= not Clk; ! wait for T2_clk; ! end process p_Clk; ! ! -- purpose: generate input signals ! -- type : combinational ! -- inputs : ! -- outputs: I1,I2,I3,I4,Di ! p_input: process ! variable count : integer := -50; -- count variable ! variable incdec : integer := 1; -- increment/decrement ! begin -- process p_input ! I1 <= conv_std_logic_vector(5*count,AnalogWidth); ! I3 <= conv_std_logic_vector(-5*count,AnalogWidth); ! I2 <= conv_std_logic_vector(count, AnalogWidth); ! I4 <= conv_std_logic_vector(-count, AnalogWidth); ! Di <= conv_std_logic_vector(count, DigitalWidth); ! ! count := count + incdec; ! if count > 50 then ! count := 50; ! incdec := -1; ! end if; ! if count < -50 then ! count := -50; ! incdec := 1; ! end if; ! ! wait for 10 ns; ! end process p_input; ! ! ! -- purpose: test datapath ! -- type : combinational ! -- inputs : ! -- outputs: ! p_Test: process ! ! begin -- process p_Test ! ! -- 1) test input(4 analog channels + digital channel) -> RAM ! -- 1.1) trough at highest rate ! ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! wait for 20 ns; ! cs <= 1; ! EnAD <= '1'; ! ThAD <= '1'; ! Latch <= '1'; ! MAAM <= MAAM_Min; ! RAMdir <= '0'; ! wait for 1000 ns; ! ! -- 1.2) sampling at lower bitrate ! ! RamDir <= '0'; ! EnAD <= '1'; ! ThAD <= '0'; ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! Cs <= 2; ! wait for 20 ns; ! Latch <= '1'; ! wait for 20*T2_Clk; ! Latch <= '0'; ! wait for T2_Clk; ! wait on Clk; ! MAAM <= MAAM_Min; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Max; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Avg1; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Avg2; ! wait for 2*T2_Clk; ! wait for 100 ns; ! ! -- 2) test RAM -> output(uC) ! -- 2.1) stored trough signal, trough PP units ! ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! wait for 20 ns; ! cs <= 3; ! EnAD <= '0'; ! ThAD <= '0'; ! Latch <= '0'; ! EnPP <= '1'; ! ThPP <= '1'; ! MAAM <= MAAM_Max; ! RAMdir <= '1'; ! wait for T2_Clk; ! RAM <= "101110000110111010101111100011010101111011000011101110010101011101001011"; ! wait on Clk; ! for i in 0 to 8 loop ! uCsel <= conv_std_logic_vector(i,4); ! wait for 2*T2_Clk; ! end loop; -- i ! RAM <= (others => 'Z'); ! ! ! ! end process p_Test; ! ! -- purpose: varify output signals ! -- type : combinational ! -- inputs : RAM ! -- outputs: ! p_varify: process (RAM,uC) ! begin -- process p_varify ! if (cs <3 and cs > 0) then ! assert RAM = t_RAM report "Signals do not match, component NOT OK!" severity WARNING; ! else ! assert uC = t_uC report "Signals do not match, component NOT OK!" severity WARNING; ! end if; ! end process p_varify; ! ! -- purpose: generating test signal t_RAM ! -- type : combinational ! -- inputs : Clk,Reset ! -- outputs: t_RAM ! p_genTest: process (Clk, Reset) ! variable help : std_logic_vector(71 downto 0); ! variable h_min, o_min : std_logic_vector(71 downto 0); ! variable h_max, o_max : std_logic_vector(71 downto 0); ! variable h_avg1,o_avg1 : std_logic_vector(71 downto 0); ! variable h_avg2,o_avg2 : std_logic_vector(71 downto 0); ! variable llc : integer := 0; -- loop count variable ! begin -- process p_genTest ! if Reset = '0' then -- asynchronous reset (active low) ! t_RAM <= (others => '0'); ! t_uC <= (others => '0'); ! help := (others => '0'); ! h_min := (others => '0'); ! h_max := (others => '0'); ! h_avg1 := (others => '0'); ! h_avg2 := (others => '0'); ! o_min := (others => '0'); ! o_max := (others => '0'); ! o_avg1 := (others => '0'); ! o_avg2 := (others => '0'); ! ! ! elsif Clk'event and Clk = '1' then -- rising clock edge ! case cs is ! when 1 => help(71 downto 40) := Di; ! help(39 downto 30) := I4; ! help(29 downto 20) := I3; ! help(19 downto 10) := I2; ! help( 9 downto 0) := I1; ! t_RAM <= help after 2*T2_Clk; ! when 2 => if llc=1 then ! ! if IEEE.std_logic_signed."<"(I1'Delayed(2*T2_Clk),h_min(9 downto 0)) then ! h_min(9 downto 0) := I1'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I2'Delayed(2*T2_Clk),h_min(19 downto 10)) then ! h_min(19 downto 10) := I2'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I3'Delayed(2*T2_Clk),h_min(29 downto 20)) then ! h_min(29 downto 20) := I3'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I4'Delayed(2*T2_Clk),h_min(39 downto 30)) then ! h_min(39 downto 30) := I4'Delayed(2*T2_Clk); ! end if; ! h_min(71 downto 40) := h_min(71 downto 40) and Di'Delayed(2*T2_Clk); ! ! if IEEE.std_logic_signed.">"(I1'Delayed(2*T2_Clk),h_max(9 downto 0)) then ! h_max(9 downto 0) := I1'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I2'Delayed(2*T2_Clk),h_max(19 downto 10)) then ! h_max(19 downto 10) := I2'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I3'Delayed(2*T2_Clk),h_max(29 downto 20)) then ! h_max(29 downto 20) := I3'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I4'Delayed(2*T2_Clk),h_max(39 downto 30)) then ! h_max(39 downto 30) := I4'Delayed(2*T2_Clk); ! end if; ! h_max(71 downto 40) := h_max(71 downto 40) or Di'Delayed(2*T2_Clk); ! ! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I2'Delayed(2*T2_Clk); ! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I1'Delayed(2*T2_Clk); ! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I4'Delayed(2*T2_Clk); ! h_avg2(35 downto 0) := h_avg2(35 downto 0) + I3'Delayed(2*T2_Clk); ! ! if Latch='1' then ! o_min := h_min; ! o_max := h_max; ! o_avg1:= h_avg1; ! o_avg2:= h_avg2; ! end if; ! ! case MAAM is ! when MAAM_Min => t_RAM <= o_min ; ! when MAAM_Max => t_RAM <= o_max ; ! when MAAM_Avg1=> t_RAM <= o_avg1; ! when MAAM_Avg2=> t_RAM <= o_avg2; ! end case; ! else ! llc:=1; -- one period delay ! end if; ! when 3 => t_uC <= RAM((conv_integer(uCsel)+1)*8-1 downto conv_integer(uCsel)*8); ! when others => null; ! end case; ! ! end if; ! end process p_genTest; ! ! end sim; --- 1,545 ---- ! ------------------------------------------------------------------------------- ! -- ! -- Author: Gerald Zach ! -- ! -- Filename: tb_CountDown.vhd ! -- ! -- Date of Creation: 09-04-2003 ! -- ! -- Description: Testbench for Datapath ! -- ! ------------------------------------------------------------------------------- ! -- ! -- Copyright (C) 2003 Gerald Zach ! -- ! -- This program is free software; you can redistribute it and/or modify ! -- it under the terms of the GNU General Public License as published by ! -- the Free Software Foundation; either version 2 of the License, or ! -- (at your option) any later version. ! -- ! -- This program is distributed in the hope that it will be useful, ! -- but WITHOUT ANY WARRANTY; without even the implied warranty of ! -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! -- GNU General Public License for more details. ! -- ! -- You should have received a copy of the GNU General Public License ! -- along with this program; if not, write to the Free Software ! -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ! -- ! ------------------------------------------------------------------------------- ! ! library IEEE; ! use IEEE.std_logic_1164.all; ! use IEEE.std_logic_arith.all; ! use IEEE.std_logic_signed."+"; ! use IEEE.std_logic_signed.">"; ! use IEEE.std_logic_signed."<"; ! use IEEE.std_logic_unsigned.conv_integer; ! use IEEE.math_real.all; ! use work.all; ! ! library work; ! use work.types_p.all; ! ! ! entity tb_Datapath is ! generic ( ! AnalogWidth : integer := 10; -- width of analog inputs ! DigitalWidth : integer := 32; -- width of digital inputs ! RAM_Width : integer := 72; -- width of data bus to RAM ! AverageWidth : integer := 36); -- width of averaged input (actually it is a sum) ! end tb_Datapath; ! ! architecture sim of tb_Datapath is ! signal Clk : std_logic := '0'; -- clock for all components ! signal Reset : std_logic := '1'; -- reset for all components LOW ACTIVE!!! ! signal I1 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel1 input ! signal I2 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel2 input ! signal I3 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel3 input ! signal I4 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel4 input ! signal Di : std_logic_vector(DigitalWidth-1 downto 0) := (others => '0'); -- digital inputs ! signal EnAD : std_logic := '0'; -- enable MAM-units at input ! signal ThAD : std_logic := '0'; -- allow inputs to pass MAM input units ! signal Latch : std_logic := '0'; -- latches hold values ! signal MAAM : MAAM_t; -- select Min/Avg1/Avg2/Max to be written to RAM or directed to MUX_uC ! signal RAMdir : std_logic := '0'; -- read/write RAM ! signal EnPP : std_logic := '0'; -- enable PP_Clk ! signal ThPP : std_logic := '0'; -- pass PP-units ! signal uCsel : std_logic_vector(3 downto 0) := (others => '0'); -- select 8 bit words -> output ! signal RAM : std_logic_vector(RAM_Width-1 downto 0); -- RAM values ! signal uC : std_logic_vector(7 downto 0); -- output to uC ! ! -- signals especially for testing ! signal t_RAM : std_logic_vector(71 downto 0) :=(others => 'Z'); -- varify RAM signal ! signal t_uC : std_logic_vector(7 downto 0); -- varify uC signal ! signal TestState : Test_t := IdlePrep; -- for testing routine ! ! constant T2_clk : time := 6.25 ns; -- half period (80MHz) ! ! component Datapath ! generic ( ! AnalogWidth : integer; -- width of analog inputs ! DigitalWidth : integer; -- width of digital inputs ! RAM_Width : integer); -- width of data bus to RAM ! port ( ! CH1_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 1 ! CH2_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 2 ! CH3_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 3 ! CH4_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 4 ! Dig_i : in std_logic_vector(DigitalWidth-1 downto 0); -- digital input channels ! ! RAM_b : inout std_logic_vector(RAM_Width -1 downto 0); -- data path to memory ! ! uC_o : out std_logic_vector(7 downto 0); -- data bus to µC ! ! Clk : in std_logic; -- clock input ! Reset : in std_logic; -- reset input ! ! En_AD_i : in std_logic; -- enable MAMs at input side ! Through_AD_i : in std_logic; -- activate "Through_i" on MAMs at input side ! Latch_AD_i : in std_logic; -- activate Latches at input side ! MAAM_AD_i : in MAAM_t; -- select which group to be routed to RAM ! ! Through_PP_i : in std_logic; -- activate "Through_i" on MAMs at output side ! En_PP_i : in std_logic; -- enable PP_Clk unit ! MAAM_PP_i : in MAAM_t; -- select which group to be routet to the µC ! uC_Select_i : in std_logic_vector( 3 downto 0); -- select 8-bit packet from 72-bit data bus ! ! RAM_Dir_i : in std_logic); -- direction of RAM access (read/write) ! ! end component; ! ! begin -- sim ! ! i_Datapath: Datapath ! generic map ( ! AnalogWidth => AnalogWidth, ! DigitalWidth => DigitalWidth, ! RAM_Width => RAM_Width) ! port map ( ! CH1_i => I1, ! CH2_i => I2, ! CH3_i => I3, ! CH4_i => I4, ! Dig_i => Di, ! RAM_b => RAM, ! uC_o => uC, ! Clk => Clk, ! Reset => Reset, ! En_AD_i => EnAD, ! Through_AD_i => ThAD, ! Latch_AD_i => Latch, ! MAAM_AD_i => MAAM , ! En_PP_i => EnPP, ! Through_PP_i => ThPP, ! MAAM_PP_i => MAAM , ! uC_Select_i => uCsel, ! RAM_Dir_i => RAMdir); ! ! -- purpose: generate Clk signal ! -- type : combinational ! -- inputs : ! -- outputs: Clk ! p_Clk: process ! begin -- process p_Clk ! Clk <= not Clk; ! wait for T2_clk; ! end process p_Clk; ! ! -- purpose: generate input signals ! -- type : combinational ! -- inputs : ! -- outputs: I1,I2,I3,I4,Di ! p_input: process ! variable count : integer := -50; -- count variable ! variable incdec : integer := 1; -- increment/decrement ! begin -- process p_input ! I1 <= conv_std_logic_vector(5*count,AnalogWidth); ! -- I3 <= conv_std_logic_vector(-5*count,AnalogWidth); ! -- I2 <= conv_std_logic_vector(count, AnalogWidth); ! -- I4 <= conv_std_logic_vector(-count, AnalogWidth); ! Di <= conv_std_logic_vector(count, DigitalWidth); ! ! ! I2 <= conv_std_logic_vector(5*count,AnalogWidth); ! I3 <= conv_std_logic_vector(5*count,AnalogWidth); ! I4 <= conv_std_logic_vector(5*count,AnalogWidth); ! ! count := count + incdec; ! if count > 50 then ! count := 50; ! incdec := -1; ! end if; ! if count < -50 then ! count := -50; ! incdec := 1; ! end if; ! ! wait for 10 ns; ! end process p_input; ! ! ! -- purpose: test datapath ! -- type : combinational ! -- inputs : ! -- outputs: ! p_Test: process ! ! begin -- process p_Test ! ! RAM <= (others => 'Z'); ! ! -- 1) test input(4 analog channels + digital channel) -> RAM ! -- 1.1) trough at highest rate ! ! ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! wait for 20 ns; ! TestState <= Test1; ! EnAD <= '1'; ! ThAD <= '1'; ! Latch <= '1'; ! MAAM <= MAAM_Min; ! RAMdir <= '0'; ! wait for 1000 ns; ! ! -- 1.2) sampling at lower bitrate ! ! RamDir <= '0'; ! EnAD <= '1'; ! ThAD <= '0'; ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! TestState <= Test2; ! wait for 20 ns; ! Latch <= '1'; ! wait for 20*T2_Clk; ! Latch <= '0'; ! wait for T2_Clk; ! wait on Clk; ! MAAM <= MAAM_Min; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Max; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Avg1; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Avg2; ! wait for 2*T2_Clk; ! wait for 100 ns; ! ! -- 2) test RAM -> output(uC) ! -- 2.1) stored trough signal, trough PP units ! ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! wait for 20 ns; ! TestState <= Test3; ! EnAD <= '0'; ! ThAD <= '0'; ! Latch <= '0'; ! EnPP <= '1'; ! ThPP <= '1'; ! MAAM <= MAAM_Min; ! RAMdir <= '1'; ! wait for T2_Clk; ! RAM <= "101110000110111010101111100011010101111011000011101110010101011101001011"; ! wait on Clk; ! for i in 0 to 8 loop ! uCsel <= conv_std_logic_vector(i,4); ! wait for 2*T2_Clk; ! end loop; -- i ! ! -- 2.2) stored MAM signal, through PP units ! ! TestState <= IdlePrep; ! uCsel <= "0000"; ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! wait for 20 ns; ! EnAD <= '0'; ! ThAD <= '0'; ! Latch <= '0'; ! EnPP <= '1'; ! ThPP <= '1'; ! RAMdir <= '1'; ! RAM <= "101110000110111010101111100011010101111011000011101110010101011101001011"; ! wait for T2_Clk; ! wait on Clk; ! for j in 1 to 4 loop ! case j is ! when 1 => MAAM <= MAAM_Min; ! when 2 => MAAM <= MAAM_Avg1; ! when 3 => MAAM <= MAAM_Avg2; ! when 4 => MAAM <= MAAM_Max; ! when others => null; ! end case; ! wait for T2_Clk; ! TestState <= Test4; ! wait for T2_Clk; ! for i in 0 to 8 loop ! uCsel <= conv_std_logic_vector(i,4); ! wait for 2*T2_Clk; ! end loop; -- i ! TestState <= IdlePrep; ! end loop; -- j ! --RAM <= (others => 'Z'); ! wait for 50 ns; ! ! -- 2.3) stored through signal, PP for 10 samples ! -- test for MIN ! TestState <= IdlePrep; ! EnPP <= '0'; ! MAAM <= MAAM_Min; ! uCsel <= "0000"; ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! TestState <= Test5; ! wait for 20 ns; ! EnAD <= '0'; ! ThAD <= '0'; ! Latch <= '0'; ! EnPP <= '1'; ! ThPP <= '0'; ! RAMdir <= '1'; ! wait on Clk; ! for i in 1 to 10 loop ! RAM( 9 downto 0) <= I1; ! RAM(19 downto 10) <= I2; ! RAM(29 downto 20) <= I3; ! RAM(39 downto 30) <= I4; ! RAM(71 downto 40) <= Di; ! wait for 2*T2_Clk; ! end loop; -- i ! EnPP <= '0'; ! wait for T2_Clk; ! for i in 0 to 8 loop ! uCsel <= conv_std_logic_vector(i,4); ! wait for 2*T2_Clk; ! end loop; -- i ! TestState <= IdlePrep; ! RAM <= (others => 'Z'); ! ! -- test for MAX ! TestState <= IdlePrep; ! EnPP <= '0'; ! MAAM <= MAAM_Max; ! uCsel <= "0000"; ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! TestState <=Test5; ! wait for 20 ns; ! EnAD <= '0'; ! ThAD <= '0'; ! Latch <= '0'; ! EnPP <= '1'; ! ThPP <= '0'; ! RAMdir <= '1'; ! wait on Clk; ! for i in 1 to 10 loop ! RAM( 9 downto 0) <= I1; ! RAM(19 downto 10) <= I2; ! RAM(29 downto 20) <= I3; ! RAM(39 downto 30) <= I4; ! RAM(71 downto 40) <= Di; ! wait for 2*T2_Clk; ! end loop; -- i ! EnPP <= '0'; ! wait for T2_Clk; ! for i in 0 to 8 loop ! uCsel <= conv_std_logic_vector(i,4); ! wait for 2*T2_Clk; ! end loop; -- i ! TestState <= IdlePrep; ! ------------------------------------------------------------------------------- ! -- tests for Avg not possible: DEMUX_PP does not allow this configuration !!! ! ------------------------------------------------------------------------------- ! wait for 100 ns; ! ! -- 2.4) stored Min/Avg1/Avg2/Max signal, PP for 10 samples ! ! -- test not possible: DEMUX_PP does not allow this configuration! ! ! end process p_Test; ! ! ! ! -- purpose: verify output signals ! -- type : combinational ! -- inputs : RAM ! -- outputs: ! p_verify: process (RAM,uC) ! begin -- process p_varify ! case TestState is ! when Test1 => assert RAM = t_RAM report "Signals do not match, component NOT OK!" severity WARNING; ! when Test2 => assert RAM = t_RAM report "Signals do not match, component NOT OK!" severity WARNING; ! when Test3 => assert uC = t_uC report "Signals do not match, component NOT OK!" severity WARNING; ! when Test4 => assert uC = t_uC report "Signals do not match, component NOT OK!" severity WARNING; ! when Test5 => if EnPP = '0' then ! assert uC = t_uC report "Signals do not match, component NOT OK!" severity WARNING; ! end if; ! when Test6 => assert uC = t_uC report "Signals do not match, component NOT OK!" severity WARNING; ! when others => null; ! end case; ! end process p_verify; ! ! ! -- purpose: generating test signal t_RAM ! -- type : combinational ! -- inputs : Clk,Reset ! -- outputs: t_RAM ! p_genTest: process (Clk, Reset) ! variable help : std_logic_vector(71 downto 0); ! variable h_min, o_min : std_logic_vector(71 downto 0); ! variable h_max, o_max : std_logic_vector(71 downto 0); ! variable h_avg1,o_avg1 : std_logic_vector(71 downto 0); ! variable h_avg2,o_avg2 : std_logic_vector(71 downto 0); ! variable llc : integer := 0; -- loop count variable ! begin -- process p_genTest ! if Reset = '0' then -- asynchronous reset (active low) ! t_RAM <= (others => '0'); ! t_uC <= (others => '0'); ! help := (others => '0'); ! h_min := (others => '0'); ! h_max := (others => '0'); ! h_avg1 := (others => '0'); ! h_avg2 := (others => '0'); ! o_min := (others => '0'); ! o_max := (others => '0'); ! o_avg1 := (others => '0'); ! o_avg2 := (others => '0'); ! ! ! elsif Clk'event and Clk = '1' then -- rising clock edge ! case TestState is ! when Test1 => help(71 downto 40) := Di; ! help(39 downto 30) := I4; ! help(29 downto 20) := I3; ! help(19 downto 10) := I2; ! help( 9 downto 0) := I1; ! t_RAM <= help after 2*T2_Clk; ! when Test2 => if llc=1 then ! ! if IEEE.std_logic_signed."<"(I1'Delayed(2*T2_Clk),h_min(9 downto 0)) then ! h_min(9 downto 0) := I1'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I2'Delayed(2*T2_Clk),h_min(19 downto 10)) then ! h_min(19 downto 10) := I2'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I3'Delayed(2*T2_Clk),h_min(29 downto 20)) then ! h_min(29 downto 20) := I3'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I4'Delayed(2*T2_Clk),h_min(39 downto 30)) then ! h_min(39 downto 30) := I4'Delayed(2*T2_Clk); ! end if; ! h_min(71 downto 40) := h_min(71 downto 40) and Di'Delayed(2*T2_Clk); ! ! if IEEE.std_logic_signed.">"(I1'Delayed(2*T2_Clk),h_max(9 downto 0)) then ! h_max(9 downto 0) := I1'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I2'Delayed(2*T2_Clk),h_max(19 downto 10)) then ! h_max(19 downto 10) := I2'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I3'Delayed(2*T2_Clk),h_max(29 downto 20)) then ! h_max(29 downto 20) := I3'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I4'Delayed(2*T2_Clk),h_max(39 downto 30)) then ! h_max(39 downto 30) := I4'Delayed(2*T2_Clk); ! end if; ! h_max(71 downto 40) := h_max(71 downto 40) or Di'Delayed(2*T2_Clk); ! ! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I2'Delayed(2*T2_Clk); ! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I1'Delayed(2*T2_Clk); ! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I4'Delayed(2*T2_Clk); ! h_avg2(35 downto 0) := h_avg2(35 downto 0) + I3'Delayed(2*T2_Clk); ! ! if Latch='1' then ! o_min := h_min; ! o_max := h_max; ! o_avg1:= h_avg1; ! o_avg2:= h_avg2; ! end if; ! ! case MAAM is ! when MAAM_Min => t_RAM <= o_min ; ! when MAAM_Max => t_RAM <= o_max ; ! when MAAM_Avg1=> t_RAM <= o_avg1; ! when MAAM_Avg2=> t_RAM <= o_avg2; ! end case; ! else ! llc:=1; -- one period delay ! end if; ! when Test3 => t_uC <= RAM((conv_integer(uCsel)+1)*8-1 downto conv_integer(uCsel)*8); ! when Test4 => t_uC <= RAM((conv_integer(uCsel)+1)*8-1 downto conv_integer(uCsel)*8); ! llc := 0; ! when Test5 => if llc =1 then ! if EnPP = '1' then ! ! if IEEE.std_logic_signed."<"(I1'Delayed(2*T2_Clk),h_min(9 downto 0)) then ! h_min(9 downto 0) := I1'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I2'Delayed(2*T2_Clk),h_min(19 downto 10)) then ! h_min(19 downto 10) := I2'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I3'Delayed(2*T2_Clk),h_min(29 downto 20)) then ! h_min(29 downto 20) := I3'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I4'Delayed(2*T2_Clk),h_min(39 downto 30)) then ! h_min(39 downto 30) := I4'Delayed(2*T2_Clk); ! end if; ! h_min(71 downto 40) := h_min(71 downto 40) and Di'Delayed(2*T2_Clk); ! ! if IEEE.std_logic_signed.">"(I1'Delayed(2*T2_Clk),h_max(9 downto 0)) then ! h_max(9 downto 0) := I1'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I2'Delayed(2*T2_Clk),h_max(19 downto 10)) then ! h_max(19 downto 10) := I2'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I3'Delayed(2*T2_Clk),h_max(29 downto 20)) then ! h_max(29 downto 20) := I3'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I4'Delayed(2*T2_Clk),h_max(39 downto 30)) then ! h_max(39 downto 30) := I4'Delayed(2*T2_Clk); ! end if; ! h_max(71 downto 40) := h_max(71 downto 40) or Di'Delayed(2*T2_Clk); ! ! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I2'Delayed(2*T2_Clk); ! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I1'Delayed(2*T2_Clk); ! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I4'Delayed(2*T2_Clk); ! h_avg2(35 downto 0) := h_avg2(35 downto 0) + I3'Delayed(2*T2_Clk); ! ! else ! o_min := h_min; ! o_max := h_max; ! o_avg1:= h_avg1; ! o_avg2:= h_avg2; ! end if; ! else ! llc:=1; ! end if; ! ! case MAAM is ! when MAAM_Min => t_RAM <= o_min ; ! when MAAM_Max => t_RAM <= o_max ; ! when MAAM_Avg1=> t_RAM <= o_avg1; ! when MAAM_Avg2=> t_RAM <= o_avg2; ! end case; ! ! if EnPP='0' then ! t_uC <= t_RAM((conv_integer(uCsel)+1)*8-1 downto conv_integer(uCsel)*8); ! end if; ! ! -- when Test6 =>; ! ! when others => null; ! end case; ! end if; ! end process p_genTest; ! ! end sim; |
From: Gerald Z. <ri...@us...> - 2003-05-08 14:48:42
|
Update of /cvsroot/dso/FPGA/src In directory sc8-pr-cvs1:/tmp/cvs-serv4048/FPGA/src Modified Files: types_p.vhd Log Message: first 5 tests running, rest not possible: DEMUX_PP must bei modified; Index: types_p.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/src/types_p.vhd,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** types_p.vhd 26 Feb 2003 10:10:10 -0000 1.2 --- types_p.vhd 8 May 2003 14:48:39 -0000 1.3 *************** *** 1,35 **** ! ------------------------------------------------------------------------------- ! -- ! -- Author: Johann Glaser ! -- ! -- Filename: types_.vhd ! -- ! -- Date of Creation: 25-02-2003 ! -- ! -- Description: Package with types. ! -- ! ------------------------------------------------------------------------------- ! -- ! -- Copyright (C) 2003 Johann Glaser ! -- ! -- This program is free software; you can redistribute it and/or modify ! -- it under the terms of the GNU General Public License as published by ! -- the Free Software Foundation; either version 2 of the License, or ! -- (at your option) any later version. ! -- ! -- This program is distributed in the hope that it will be useful, ! -- but WITHOUT ANY WARRANTY; without even the implied warranty of ! -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! -- GNU General Public License for more details. ! -- ! -- You should have received a copy of the GNU General Public License ! -- along with this program; if not, write to the Free Software ! -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ! -- ! ------------------------------------------------------------------------------- ! ! package types_p is ! ! type MAAM_t is (MAAM_Min,MAAM_Avg1,MAAM_Avg2,MAAM_Max); -- MUX selection which data group for the RAM ! ! end types_p; --- 1,36 ---- ! ------------------------------------------------------------------------------- ! -- ! -- Author: Johann Glaser ! -- ! -- Filename: types_.vhd ! -- ! -- Date of Creation: 25-02-2003 ! -- ! -- Description: Package with types. ! -- ! ------------------------------------------------------------------------------- ! -- ! -- Copyright (C) 2003 Johann Glaser ! -- ! -- This program is free software; you can redistribute it and/or modify ! -- it under the terms of the GNU General Public License as published by ! -- the Free Software Foundation; either version 2 of the License, or ! -- (at your option) any later version. ! -- ! -- This program is distributed in the hope that it will be useful, ! -- but WITHOUT ANY WARRANTY; without even the implied warranty of ! -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! -- GNU General Public License for more details. ! -- ! -- You should have received a copy of the GNU General Public License ! -- along with this program; if not, write to the Free Software ! -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ! -- ! ------------------------------------------------------------------------------- ! ! package types_p is ! ! type MAAM_t is (MAAM_Min,MAAM_Avg1,MAAM_Avg2,MAAM_Max); -- MUX selection which data group for the RAM ! type Test_t is (IdlePrep,Test1,Test2,Test3,Test4,Test5,Test6); -- for tb_Datapath ! ! end types_p; |
From: Gerald Z. <ri...@us...> - 2003-04-30 11:26:35
|
Update of /cvsroot/dso/FPGA/tb In directory sc8-pr-cvs1:/tmp/cvs-serv31242/FPGA/tb Modified Files: tb_Datapath.vhd Log Message: Index: tb_Datapath.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/tb/tb_Datapath.vhd,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** tb_Datapath.vhd 29 Apr 2003 14:28:05 -0000 1.4 --- tb_Datapath.vhd 30 Apr 2003 11:26:27 -0000 1.5 *************** *** 33,36 **** --- 33,39 ---- use IEEE.std_logic_arith.all; use IEEE.std_logic_signed."+"; + use IEEE.std_logic_signed.">"; + use IEEE.std_logic_signed."<"; + use IEEE.std_logic_unsigned.conv_integer; use IEEE.math_real.all; use work.all; *************** *** 62,71 **** signal RAMdir : std_logic := '0'; -- read/write RAM signal EnPP : std_logic := '0'; -- enable PP_Clk ! signal ThPP : std_logic := '0'; -- enable PP-units signal uCsel : std_logic_vector(3 downto 0) := (others => '0'); -- select 8 bit words -> output signal RAM : std_logic_vector(RAM_Width-1 downto 0); -- RAM values signal uC : std_logic_vector(7 downto 0); -- output to uC ! signal t_RAM : std_logic_vector(71 downto 0); -- varify RAM signal signal cs : integer := 0; -- for testing routine --- 65,75 ---- signal RAMdir : std_logic := '0'; -- read/write RAM signal EnPP : std_logic := '0'; -- enable PP_Clk ! signal ThPP : std_logic := '0'; -- pass PP-units signal uCsel : std_logic_vector(3 downto 0) := (others => '0'); -- select 8 bit words -> output signal RAM : std_logic_vector(RAM_Width-1 downto 0); -- RAM values signal uC : std_logic_vector(7 downto 0); -- output to uC ! signal t_RAM : std_logic_vector(71 downto 0) :=(others => 'Z'); -- varify RAM signal ! signal t_uC : std_logic_vector(7 downto 0); -- varify uC signal signal cs : integer := 0; -- for testing routine *************** *** 149,152 **** --- 153,157 ---- p_input: process variable count : integer := -50; -- count variable + variable incdec : integer := 1; -- increment/decrement begin -- process p_input I1 <= conv_std_logic_vector(5*count,AnalogWidth); *************** *** 156,163 **** Di <= conv_std_logic_vector(count, DigitalWidth); ! count := count + 1; if count > 50 then count := 50; end if; wait for 10 ns; end process p_input; --- 161,174 ---- Di <= conv_std_logic_vector(count, DigitalWidth); ! count := count + incdec; if count > 50 then count := 50; + incdec := -1; end if; + if count < -50 then + count := -50; + incdec := 1; + end if; + wait for 10 ns; end process p_input; *************** *** 172,176 **** begin -- process p_Test ! -- 1) test input -> RAM -- 1.1) trough at highest rate --- 183,187 ---- begin -- process p_Test ! -- 1) test input(4 analog channels + digital channel) -> RAM -- 1.1) trough at highest rate *************** *** 185,189 **** MAAM <= MAAM_Min; RAMdir <= '0'; ! wait for 2000 ns; -- 1.2) sampling at lower bitrate --- 196,200 ---- MAAM <= MAAM_Min; RAMdir <= '0'; ! wait for 1000 ns; -- 1.2) sampling at lower bitrate *************** *** 200,204 **** wait for 20*T2_Clk; Latch <= '0'; ! wait for 10*T2_Clk; MAAM <= MAAM_Min; wait for 2*T2_Clk; --- 211,216 ---- wait for 20*T2_Clk; Latch <= '0'; ! wait for T2_Clk; ! wait on Clk; MAAM <= MAAM_Min; wait for 2*T2_Clk; *************** *** 211,214 **** --- 223,250 ---- wait for 100 ns; + -- 2) test RAM -> output(uC) + -- 2.1) stored trough signal, trough PP units + + Reset <= '0'; + wait for 20 ns; + Reset <= '1'; + wait for 20 ns; + cs <= 3; + EnAD <= '0'; + ThAD <= '0'; + Latch <= '0'; + EnPP <= '1'; + ThPP <= '1'; + MAAM <= MAAM_Max; + RAMdir <= '1'; + wait for T2_Clk; + RAM <= "101110000110111010101111100011010101111011000011101110010101011101001011"; + wait on Clk; + for i in 0 to 8 loop + uCsel <= conv_std_logic_vector(i,4); + wait for 2*T2_Clk; + end loop; -- i + RAM <= (others => 'Z'); + *************** *** 219,227 **** -- inputs : RAM -- outputs: ! p_varify: process (RAM) begin -- process p_varify ! ! assert RAM = t_RAM report "signals do not match!" severity WARNING; ! end process p_varify; --- 255,265 ---- -- inputs : RAM -- outputs: ! p_varify: process (RAM,uC) begin -- process p_varify ! if (cs <3 and cs > 0) then ! assert RAM = t_RAM report "Signals do not match, component NOT OK!" severity WARNING; ! else ! assert uC = t_uC report "Signals do not match, component NOT OK!" severity WARNING; ! end if; end process p_varify; *************** *** 236,243 **** variable h_avg1,o_avg1 : std_logic_vector(71 downto 0); variable h_avg2,o_avg2 : std_logic_vector(71 downto 0); begin -- process p_genTest if Reset = '0' then -- asynchronous reset (active low) ! t_RAM <= (others => '0'); ! help := (others => '0'); h_min := (others => '0'); h_max := (others => '0'); --- 274,283 ---- variable h_avg1,o_avg1 : std_logic_vector(71 downto 0); variable h_avg2,o_avg2 : std_logic_vector(71 downto 0); + variable llc : integer := 0; -- loop count variable begin -- process p_genTest if Reset = '0' then -- asynchronous reset (active low) ! t_RAM <= (others => '0'); ! t_uC <= (others => '0'); ! help := (others => '0'); h_min := (others => '0'); h_max := (others => '0'); *************** *** 249,252 **** --- 289,293 ---- o_avg2 := (others => '0'); + elsif Clk'event and Clk = '1' then -- rising clock edge case cs is *************** *** 257,308 **** help( 9 downto 0) := I1; t_RAM <= help after 2*T2_Clk; ! when 2 => ! if I1 < h_min(9 downto 0) then ! h_min(9 downto 0) := I1; end if; ! if I2 < h_min(19 downto 10) then ! h_min(19 downto 10) := I2; end if; ! if I3 < h_min(29 downto 20) then ! h_min(29 downto 20) := I3; end if; ! if I4 < h_min(39 downto 30) then ! h_min(39 downto 30) := I4; end if; ! h_min(71 downto 40) := h_min(31 downto 0) and Di; ! if I1 > h_max(9 downto 0) then ! h_min(9 downto 0) := I1; end if; ! if I2 > h_max(19 downto 10) then ! h_min(19 downto 10) := I2; end if; ! if I3 > h_max(29 downto 20) then ! h_min(29 downto 20) := I3; end if; ! if I4 > h_max(39 downto 30) then ! h_min(39 downto 30) := I4; end if; ! h_max(71 downto 40) := h_max(31 downto 0) or Di; ! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I2; ! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I1; ! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I4; ! h_avg2(35 downto 0) := h_avg2(35 downto 0) + I3; ! if Latch='0' then ! o_min := h_min; ! o_max := h_max; ! o_avg1:= h_avg1; ! o_avg2:= h_avg2; ! end if; ! case MAAM is ! when MAAM_Min => t_RAM <= o_min; ! when MAAM_Max => t_RAM <= o_max; ! when MAAM_Avg1=> t_RAM <= o_avg1; ! when MAAM_Avg2=> t_RAM <= o_avg2; ! end case; ! when others => null; end case; --- 298,353 ---- help( 9 downto 0) := I1; t_RAM <= help after 2*T2_Clk; ! when 2 => if llc=1 then ! ! if IEEE.std_logic_signed."<"(I1'Delayed(2*T2_Clk),h_min(9 downto 0)) then ! h_min(9 downto 0) := I1'Delayed(2*T2_Clk); end if; ! if IEEE.std_logic_signed."<"(I2'Delayed(2*T2_Clk),h_min(19 downto 10)) then ! h_min(19 downto 10) := I2'Delayed(2*T2_Clk); end if; ! if IEEE.std_logic_signed."<"(I3'Delayed(2*T2_Clk),h_min(29 downto 20)) then ! h_min(29 downto 20) := I3'Delayed(2*T2_Clk); end if; ! if IEEE.std_logic_signed."<"(I4'Delayed(2*T2_Clk),h_min(39 downto 30)) then ! h_min(39 downto 30) := I4'Delayed(2*T2_Clk); end if; ! h_min(71 downto 40) := h_min(71 downto 40) and Di'Delayed(2*T2_Clk); ! if IEEE.std_logic_signed.">"(I1'Delayed(2*T2_Clk),h_max(9 downto 0)) then ! h_max(9 downto 0) := I1'Delayed(2*T2_Clk); end if; ! if IEEE.std_logic_signed.">"(I2'Delayed(2*T2_Clk),h_max(19 downto 10)) then ! h_max(19 downto 10) := I2'Delayed(2*T2_Clk); end if; ! if IEEE.std_logic_signed.">"(I3'Delayed(2*T2_Clk),h_max(29 downto 20)) then ! h_max(29 downto 20) := I3'Delayed(2*T2_Clk); end if; ! if IEEE.std_logic_signed.">"(I4'Delayed(2*T2_Clk),h_max(39 downto 30)) then ! h_max(39 downto 30) := I4'Delayed(2*T2_Clk); end if; ! h_max(71 downto 40) := h_max(71 downto 40) or Di'Delayed(2*T2_Clk); ! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I2'Delayed(2*T2_Clk); ! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I1'Delayed(2*T2_Clk); ! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I4'Delayed(2*T2_Clk); ! h_avg2(35 downto 0) := h_avg2(35 downto 0) + I3'Delayed(2*T2_Clk); ! if Latch='1' then ! o_min := h_min; ! o_max := h_max; ! o_avg1:= h_avg1; ! o_avg2:= h_avg2; ! end if; ! case MAAM is ! when MAAM_Min => t_RAM <= o_min ; ! when MAAM_Max => t_RAM <= o_max ; ! when MAAM_Avg1=> t_RAM <= o_avg1; ! when MAAM_Avg2=> t_RAM <= o_avg2; ! end case; ! else ! llc:=1; -- one period delay ! end if; ! when 3 => t_uC <= RAM((conv_integer(uCsel)+1)*8-1 downto conv_integer(uCsel)*8); when others => null; end case; |
From: Gerald Z. <ri...@us...> - 2003-04-30 11:26:32
|
Update of /cvsroot/dso/FPGA/msim In directory sc8-pr-cvs1:/tmp/cvs-serv31242/FPGA/msim Modified Files: compile.tcl Log Message: Index: compile.tcl =================================================================== RCS file: /cvsroot/dso/FPGA/msim/compile.tcl,v retrieving revision 1.14 retrieving revision 1.15 diff -C2 -d -r1.14 -r1.15 *** compile.tcl 29 Apr 2003 14:28:03 -0000 1.14 --- compile.tcl 30 Apr 2003 11:26:27 -0000 1.15 *************** *** 32,35 **** --- 32,36 ---- vcom -work work ../src/Max_D_.vhd vcom -work work ../src/Min_D_.vhd + vcom -work work ../src/PP_Clk_.vhd # compile architectures *************** *** 54,57 **** --- 55,59 ---- vcom -work work ../src/Min_D_rtl.vhd vcom -work work ../src/Max_D_rtl.vhd + vcom -work work ../src/PP_Clk_rtl.vhd vcom -93 -work work ../src/Datapath_struc.vhd |
From: Gerald Z. <ri...@us...> - 2003-04-29 14:29:16
|
Update of /cvsroot/dso/FPGA/src In directory sc8-pr-cvs1:/tmp/cvs-serv1125/FPGA/src Modified Files: Avg_A_rtl.vhd Log Message: Index: Avg_A_rtl.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/src/Avg_A_rtl.vhd,v retrieving revision 1.10 retrieving revision 1.11 diff -C2 -d -r1.10 -r1.11 *** Avg_A_rtl.vhd 29 Apr 2003 14:28:05 -0000 1.10 --- Avg_A_rtl.vhd 29 Apr 2003 14:29:11 -0000 1.11 *************** *** 46,50 **** variable Avg_var : std_logic_vector(WidthOut-1 downto 0); begin ! if Reset = '1' then -- asynchronous reset (active low) Avg_var := (others => '0'); elsif Clk'event and Clk = '1' then -- rising clock edge --- 46,50 ---- variable Avg_var : std_logic_vector(WidthOut-1 downto 0); begin ! if Reset = '0' then -- asynchronous reset (active low) Avg_var := (others => '0'); elsif Clk'event and Clk = '1' then -- rising clock edge |
From: Gerald Z. <ri...@us...> - 2003-04-29 14:28:10
|
Update of /cvsroot/dso/FPGA/tb In directory sc8-pr-cvs1:/tmp/cvs-serv456/FPGA/tb Modified Files: tb_Datapath.vhd Log Message: Index: tb_Datapath.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/tb/tb_Datapath.vhd,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** tb_Datapath.vhd 18 Apr 2003 09:27:32 -0000 1.3 --- tb_Datapath.vhd 29 Apr 2003 14:28:05 -0000 1.4 *************** *** 50,54 **** architecture sim of tb_Datapath is signal Clk : std_logic := '0'; -- clock for all components ! signal Reset : std_logic := '0'; -- reset for all components signal I1 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel1 input signal I2 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel2 input --- 50,54 ---- architecture sim of tb_Datapath is signal Clk : std_logic := '0'; -- clock for all components ! signal Reset : std_logic := '1'; -- reset for all components LOW ACTIVE!!! signal I1 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel1 input signal I2 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel2 input *************** *** 155,158 **** --- 155,159 ---- I4 <= conv_std_logic_vector(-count, AnalogWidth); Di <= conv_std_logic_vector(count, DigitalWidth); + count := count + 1; if count > 50 then *************** *** 174,181 **** -- 1.1) trough at highest rate - Reset <= '1'; - wait for 20 ns; Reset <= '0'; wait for 20 ns; cs <= 1; EnAD <= '1'; --- 175,182 ---- -- 1.1) trough at highest rate Reset <= '0'; wait for 20 ns; + Reset <= '1'; + wait for 20 ns; cs <= 1; EnAD <= '1'; *************** *** 187,198 **** -- 1.2) sampling at lower bitrate ! Reset <= '1'; ! wait for 20 ns; ! Reset <= '0'; ! wait for 20 ns; ! cs <= 2; RamDir <= '0'; EnAD <= '1'; ThAD <= '0'; Latch <= '1'; wait for 20*T2_Clk; --- 188,200 ---- -- 1.2) sampling at lower bitrate ! RamDir <= '0'; EnAD <= '1'; ThAD <= '0'; + Reset <= '0'; + wait for 20 ns; + Reset <= '1'; + Cs <= 2; + wait for 20 ns; Latch <= '1'; wait for 20*T2_Clk; *************** *** 207,211 **** MAAM <= MAAM_Avg2; wait for 2*T2_Clk; ! --- 209,213 ---- MAAM <= MAAM_Avg2; wait for 2*T2_Clk; ! wait for 100 ns; *************** *** 249,292 **** elsif Clk'event and Clk = '1' then -- rising clock edge case cs is ! when 1 => help(71 downto 62) := I1; ! help(61 downto 52) := I2; ! help(51 downto 42) := I3; ! help(41 downto 32) := I4; ! help(31 downto 0) := Di; ! t_RAM <= help after 2*T2_Clk; ! when 2 => if I1 < h_min(71 downto 62) then ! h_min(71 downto 62) := I1; ! end if; ! if I2 < h_min(61 downto 52) then ! h_min(61 downto 52) := I2; ! end if; ! if I3 < h_min(51 downto 42) then ! h_min(51 downto 42) := I3; ! end if; ! if I4 < h_min(41 downto 32) then ! h_min(41 downto 32) := I4; ! end if; ! h_min(31 downto 0) := h_min(31 downto 0) and Di; ! if I1 > h_max(71 downto 62) then ! h_min(71 downto 62) := I1; ! end if; ! if I2 > h_max(61 downto 52) then ! h_min(61 downto 52) := I2; ! end if; ! if I3 > h_max(51 downto 42) then ! h_min(51 downto 42) := I3; ! end if; ! if I4 > h_max(41 downto 32) then ! h_min(41 downto 32) := I4; ! end if; ! h_max(31 downto 0) := h_max(31 downto 0) or Di; ! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I1; ! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I2; ! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I3; ! h_avg2(35 downto 0) := h_avg2(36 downto 0) + I4; ! if Latch='1' then o_min := h_min; o_max := h_max; --- 251,295 ---- elsif Clk'event and Clk = '1' then -- rising clock edge case cs is ! when 1 => help(71 downto 40) := Di; ! help(39 downto 30) := I4; ! help(29 downto 20) := I3; ! help(19 downto 10) := I2; ! help( 9 downto 0) := I1; ! t_RAM <= help after 2*T2_Clk; ! when 2 => ! if I1 < h_min(9 downto 0) then ! h_min(9 downto 0) := I1; ! end if; ! if I2 < h_min(19 downto 10) then ! h_min(19 downto 10) := I2; ! end if; ! if I3 < h_min(29 downto 20) then ! h_min(29 downto 20) := I3; ! end if; ! if I4 < h_min(39 downto 30) then ! h_min(39 downto 30) := I4; ! end if; ! h_min(71 downto 40) := h_min(31 downto 0) and Di; ! if I1 > h_max(9 downto 0) then ! h_min(9 downto 0) := I1; ! end if; ! if I2 > h_max(19 downto 10) then ! h_min(19 downto 10) := I2; ! end if; ! if I3 > h_max(29 downto 20) then ! h_min(29 downto 20) := I3; ! end if; ! if I4 > h_max(39 downto 30) then ! h_min(39 downto 30) := I4; ! end if; ! h_max(71 downto 40) := h_max(31 downto 0) or Di; ! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I2; ! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I1; ! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I4; ! h_avg2(35 downto 0) := h_avg2(35 downto 0) + I3; ! if Latch='0' then o_min := h_min; o_max := h_max; |
From: Gerald Z. <ri...@us...> - 2003-04-29 14:28:10
|
Update of /cvsroot/dso/FPGA/src In directory sc8-pr-cvs1:/tmp/cvs-serv456/FPGA/src Modified Files: Avg_A_rtl.vhd Log Message: Index: Avg_A_rtl.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/src/Avg_A_rtl.vhd,v retrieving revision 1.9 retrieving revision 1.10 diff -C2 -d -r1.9 -r1.10 *** Avg_A_rtl.vhd 8 Apr 2003 13:25:15 -0000 1.9 --- Avg_A_rtl.vhd 29 Apr 2003 14:28:05 -0000 1.10 *************** *** 46,50 **** variable Avg_var : std_logic_vector(WidthOut-1 downto 0); begin ! if Reset = '0' then -- asynchronous reset (active low) Avg_var := (others => '0'); elsif Clk'event and Clk = '1' then -- rising clock edge --- 46,50 ---- variable Avg_var : std_logic_vector(WidthOut-1 downto 0); begin ! if Reset = '1' then -- asynchronous reset (active low) Avg_var := (others => '0'); elsif Clk'event and Clk = '1' then -- rising clock edge |