[Dso-cvs] FPGA/tb tb_Datapath.vhd,1.6,1.7

[Johann G. <han...@us...>]

Update of /cvsroot/dso/FPGA/tb
In directory sc8-pr-cvs1:/tmp/cvs-serv26131/tb

Modified Files:
	tb_Datapath.vhd 
Log Message:
added "-93" to _all_ "vcom" commands in msim/compile.tcl
updated TODO
corrected DEMUX_PP to use the "MAM_i" input which determines wether the data
  from RAM was MAM'ed or not. Corrected Datapath and testbench to reflect
  these changes.
Moved type "Test_t" from types_p.vhd to tb_Datapath.vhd.


Index: tb_Datapath.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/tb/tb_Datapath.vhd,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** tb_Datapath.vhd	8 May 2003 14:48:39 -0000	1.6
--- tb_Datapath.vhd	14 May 2003 08:38:00 -0000	1.7
***************
*** 29,32 ****
--- 29,34 ----
  -------------------------------------------------------------------------------
  
+ -- run for >2700ns
+   
  library IEEE; 
  use IEEE.std_logic_1164.all;
***************
*** 63,66 ****
--- 65,69 ----
    signal Latch  : std_logic                                 := '0';             -- latches hold values
    signal MAAM   : MAAM_t;                                                       -- select Min/Avg1/Avg2/Max to be written to RAM or directed to MUX_uC
+   signal MAM_PP : std_logic                                 := '1';             -- tell DEMUX_PP wether data from RAM was MAM'ed or not
    signal RAMdir : std_logic                                 := '0';             -- read/write RAM
    signal EnPP   : std_logic                                 := '0';             -- enable PP_Clk
***************
*** 70,73 ****
--- 73,78 ----
    signal uC     : std_logic_vector(7 downto 0);  -- output to uC
  
+   type Test_t is (IdlePrep,Test1,Test2,Test3,Test4,Test5,Test6);  -- for tb_Datapath
+   
  -- signals especially for testing
    signal t_RAM  : std_logic_vector(71 downto 0)             :=(others => 'Z');  -- varify RAM signal
***************
*** 100,107 ****
          Latch_AD_i   : in    std_logic;     -- activate Latches at input side
          MAAM_AD_i    : in    MAAM_t;        -- select which group to be routed to RAM
!     
          Through_PP_i : in    std_logic;     -- activate "Through_i" on MAMs at output side
          En_PP_i      : in    std_logic;     -- enable PP_Clk unit
          MAAM_PP_i    : in    MAAM_t;        -- select which group to be routet to the µC
          uC_Select_i  : in    std_logic_vector( 3 downto 0);  -- select 8-bit packet from 72-bit data bus
      
--- 105,113 ----
          Latch_AD_i   : in    std_logic;     -- activate Latches at input side
          MAAM_AD_i    : in    MAAM_t;        -- select which group to be routed to RAM
! 
          Through_PP_i : in    std_logic;     -- activate "Through_i" on MAMs at output side
          En_PP_i      : in    std_logic;     -- enable PP_Clk unit
          MAAM_PP_i    : in    MAAM_t;        -- select which group to be routet to the µC
+         MAM_PP_i     : in    std_logic;     -- tell DEMUX_PP if data from RAM was MAM'ed or not
          uC_Select_i  : in    std_logic_vector( 3 downto 0);  -- select 8-bit packet from 72-bit data bus
      
***************
*** 130,137 ****
        Through_AD_i => ThAD,
        Latch_AD_i   => Latch,
!       MAAM_AD_i    => MAAM   ,
        En_PP_i      => EnPP,
        Through_PP_i => ThPP,
!       MAAM_PP_i    => MAAM   ,
        uC_Select_i  => uCsel,
        RAM_Dir_i    => RAMdir);
--- 136,144 ----
        Through_AD_i => ThAD,
        Latch_AD_i   => Latch,
!       MAAM_AD_i    => MAAM,
        En_PP_i      => EnPP,
        Through_PP_i => ThPP,
!       MAAM_PP_i    => MAAM,
!       MAM_PP_i     => MAM_PP,
        uC_Select_i  => uCsel,
        RAM_Dir_i    => RAMdir);
***************
*** 366,370 ****
  
  -- test not possible: DEMUX_PP does not allow this configuration!
!       
    end process p_Test;
  
--- 373,380 ----
  
  -- test not possible: DEMUX_PP does not allow this configuration!
! 
!     -- TODO: write this test, it is now possible with the signal "MAM_PP"
!     
!     assert false report "Ready" severity FAILURE;
    end process p_Test;