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From: Gerald Z. <ri...@us...> - 2003-04-29 14:28:08
|
Update of /cvsroot/dso/FPGA/msim In directory sc8-pr-cvs1:/tmp/cvs-serv456/FPGA/msim Modified Files: compile.tcl Log Message: Index: compile.tcl =================================================================== RCS file: /cvsroot/dso/FPGA/msim/compile.tcl,v retrieving revision 1.13 retrieving revision 1.14 diff -C2 -d -r1.13 -r1.14 *** compile.tcl 15 Apr 2003 13:00:48 -0000 1.13 --- compile.tcl 29 Apr 2003 14:28:03 -0000 1.14 *************** *** 25,28 **** --- 25,29 ---- vcom -work work ../src/MUX_4_N_.vhd vcom -work work ../src/MUX_AD_.vhd + vcom -work work ../src/Datapath_.vhd vcom -work work ../src/MUX_RAM_.vhd vcom -work work ../src/MUX_uC_.vhd *************** *** 33,37 **** # compile architectures ! vcom -work work ../src/Avg_A_.vhd vcom -work work ../src/DEMUX_PP_rtl.vhd vcom -work work ../src/Join_Avg_struc.vhd --- 34,38 ---- # compile architectures ! vcom -work work ../src/Avg_A_rtl.vhd vcom -work work ../src/DEMUX_PP_rtl.vhd vcom -work work ../src/Join_Avg_struc.vhd *************** *** 44,48 **** vcom -work work ../src/MAM_D_P_struc.vhd vcom -work work ../src/MUX_4_N_rtl.vhd ! vcom -work work ../src/MUX_AD_struc.vhd vcom -work work ../src/MUX_RAM_rtl.vhd vcom -work work ../src/MUX_uC_rtl.vhd --- 45,49 ---- vcom -work work ../src/MAM_D_P_struc.vhd vcom -work work ../src/MUX_4_N_rtl.vhd ! vcom -93 -work work ../src/MUX_AD_struc.vhd vcom -work work ../src/MUX_RAM_rtl.vhd vcom -work work ../src/MUX_uC_rtl.vhd *************** *** 51,54 **** --- 52,58 ---- vcom -work work ../src/Latch_A_rtl.vhd vcom -work work ../src/Latch_D_rtl.vhd + vcom -work work ../src/Min_D_rtl.vhd + vcom -work work ../src/Max_D_rtl.vhd + vcom -93 -work work ../src/Datapath_struc.vhd # compile testbenches *************** *** 64,65 **** --- 68,70 ---- vcom -work work ../tb/tb_MUX_AD.vhd vcom -work work ../tb/tb_MAM_A.vhd + vcom -work work ../tb/tb_Datapath.vhd \ No newline at end of file |
|
From: Gerald Z. <ri...@us...> - 2003-04-18 09:27:38
|
Update of /cvsroot/dso/FPGA/tb In directory sc8-pr-cvs1:/tmp/cvs-serv18709 Modified Files: tb_Datapath.vhd Log Message: testing routines appended but not complete not simulated -> the 2 known files could not be compiled yet Index: tb_Datapath.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/tb/tb_Datapath.vhd,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** tb_Datapath.vhd 15 Apr 2003 13:00:54 -0000 1.2 --- tb_Datapath.vhd 18 Apr 2003 09:27:32 -0000 1.3 *************** *** 1,194 **** ! ------------------------------------------------------------------------------- ! -- ! -- Author: Gerald Zach ! -- ! -- Filename: tb_CountDown.vhd ! -- ! -- Date of Creation: 09-04-2003 ! -- ! -- Description: Testbench for Datapath ! -- ! ------------------------------------------------------------------------------- ! -- ! -- Copyright (C) 2003 Gerald Zach ! -- ! -- This program is free software; you can redistribute it and/or modify ! -- it under the terms of the GNU General Public License as published by ! -- the Free Software Foundation; either version 2 of the License, or ! -- (at your option) any later version. ! -- ! -- This program is distributed in the hope that it will be useful, ! -- but WITHOUT ANY WARRANTY; without even the implied warranty of ! -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! -- GNU General Public License for more details. ! -- ! -- You should have received a copy of the GNU General Public License ! -- along with this program; if not, write to the Free Software ! -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ! -- ! ------------------------------------------------------------------------------- ! ! library IEEE; ! use IEEE.std_logic_1164.all; ! use IEEE.std_logic_arith.all; ! use IEEE.math_real.all; ! use work.all; ! ! library work; ! use work.types_p.all; ! ! ! entity tb_Datapath is ! generic ( ! AnalogWidth : integer := 10; -- width of analog inputs ! DigitalWidth : integer := 32; -- width of digital inputs ! RAM_Width : integer := 72; -- width of data bus to RAM ! AverageWidth : integer := 36); -- width of averaged input (actually it is a sum) ! end tb_Datapath; ! ! architecture sim of tb_Datapath is ! signal Clk : std_logic := '0'; -- clock for all components ! signal Reset : std_logic := '0'; -- reset for all components ! signal I1 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel1 input ! signal I2 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel2 input ! signal I3 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel3 input ! signal I4 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel4 input ! signal Di : std_logic_vector(DigitalWidth-1 downto 0) := (others => '0'); -- digital inputs ! signal EnAD : std_logic := '0'; -- enable MAM-units at input ! signal ThAD : std_logic := '0'; -- allow inputs to pass MAM input units ! signal Latch : std_logic := '0'; -- latches hold values ! signal MAAM : MAAM_t; -- select Min/Avg1/Avg2/Max to be written to RAM or directed to MUX_uC ! signal RAMdir : std_logic := '0'; -- read/write RAM ! signal EnPP : std_logic := '0'; -- enable PP_Clk ! signal ThPP : std_logic := '0'; -- enable PP-units ! signal uCsel : std_logic_vector(3 downto 0) := (others => '0'); -- select 8 bit words -> output ! signal RAM : std_logic_vector(RAM_Width-1 downto 0); -- RAM values ! signal uC : std_logic_vector(7 downto 0); -- output to uC ! ! constant T2_clk : time := 6.26 ns; -- half period (80MHz) ! ! component Datapath ! generic ( ! AnalogWidth : integer; -- width of analog inputs ! DigitalWidth : integer; -- width of digital inputs ! RAM_Width : integer); -- width of data bus to RAM ! port ( ! CH1_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 1 ! CH2_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 2 ! CH3_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 3 ! CH4_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 4 ! Dig_i : in std_logic_vector(DigitalWidth-1 downto 0); -- digital input channels ! ! RAM_b : inout std_logic_vector(RAM_Width -1 downto 0); -- data path to memory ! ! uC_o : out std_logic_vector(7 downto 0); -- data bus to µC ! ! Clk : in std_logic; -- clock input ! Reset : in std_logic; -- reset input ! ! En_AD_i : in std_logic; -- enable MAMs at input side ! Through_AD_i : in std_logic; -- activate "Through_i" on MAMs at input side ! Latch_AD_i : in std_logic; -- activate Latches at input side ! MAAM_AD_i : in MAAM_t; -- select which group to be routed to RAM ! ! Through_PP_i : in std_logic; -- activate "Through_i" on MAMs at output side ! En_PP_i : in std_logic; -- enable PP_Clk unit ! MAAM_PP_i : in MAAM_t; -- select which group to be routet to the µC ! uC_Select_i : in std_logic_vector( 3 downto 0); -- select 8-bit packet from 72-bit data bus ! ! RAM_Dir_i : in std_logic); -- direction of RAM access (read/write) ! ! --constant AverageWidth : integer: = AverageWidth ; -- width of averaged input (actually it is a sum) ! end component; ! ! begin -- sim ! ! i_Datapath: Datapath ! generic map ( ! AnalogWidth => AnalogWidth, ! DigitalWidth => DigitalWidth, ! RAM_Width => RAM_Width) ! port map ( ! CH1_i => I1, ! CH2_i => I2, ! CH3_i => I3, ! CH4_i => I4, ! Dig_i => Di, ! RAM_b => RAM, ! uC_o => uC, ! Clk => Clk, ! Reset => Reset, ! En_AD_i => EnAD, ! Through_AD_i => ThAD, ! Latch_AD_i => Latch, ! MAAM_AD_i => MAAM , ! En_PP_i => EnPP, ! Through_PP_i => ThPP, ! MAAM_PP_i => MAAM , ! uC_Select_i => uCsel, ! RAM_Dir_i => RAMdir); ! ! -- purpose: generate Clk signal ! -- type : combinational ! -- inputs : ! -- outputs: Clk ! p_Clk: process ! begin -- process p_Clk ! Clk <= not Clk; ! wait for T2_clk; ! end process p_Clk; ! ! -- purpose: generate input signals ! -- type : combinational ! -- inputs : ! -- outputs: I1,I2,I3,I4,Di ! p_input: process ! variable count : integer := -50; -- count variable ! begin -- process p_input ! I1 <= conv_std_logic_vector(count/10,AnalogWidth); ! I3 <= I1; ! I2 <= conv_std_logic_vector(count, AnalogWidth); ! I4 <= I2; ! Di <= conv_std_logic_vector(count, DigitalWidth); ! count := count + 1; ! if count > 50 then ! count := 50; ! end if; ! wait for 10 ns; ! end process p_input; ! ! -- 1) test input -> RAM ! -- 1.1) trough at highest rate ! ! -- purpose: test datapath ! -- type : combinational ! -- inputs : ! -- outputs: ! p_Test: process ! ! begin -- process p_Test ! Reset <= '1'; ! wait for 20 ns; ! Reset <= '0'; ! wait for 20 ns; ! EnAD <= '1'; ! ThAD <= '1'; ! Latch <= '1'; ! MAAM <= MAAM_Min; ! RAMdir <= '0'; ! wait for 5000 ns; ! ! end process p_Test; ! ! ! ! ! ! ! ------------------------------------------------------------------------------- ! -- ! -- insert further processes for testing *Datapath* ! -- ! ------------------------------------------------------------------------------- ! ! end sim; --- 1,310 ---- ! ------------------------------------------------------------------------------- ! -- ! -- Author: Gerald Zach ! -- ! -- Filename: tb_CountDown.vhd ! -- ! -- Date of Creation: 09-04-2003 ! -- ! -- Description: Testbench for Datapath ! -- ! ------------------------------------------------------------------------------- ! -- ! -- Copyright (C) 2003 Gerald Zach ! -- ! -- This program is free software; you can redistribute it and/or modify ! -- it under the terms of the GNU General Public License as published by ! -- the Free Software Foundation; either version 2 of the License, or ! -- (at your option) any later version. ! -- ! -- This program is distributed in the hope that it will be useful, ! -- but WITHOUT ANY WARRANTY; without even the implied warranty of ! -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! -- GNU General Public License for more details. ! -- ! -- You should have received a copy of the GNU General Public License ! -- along with this program; if not, write to the Free Software ! -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ! -- ! ------------------------------------------------------------------------------- ! ! library IEEE; ! use IEEE.std_logic_1164.all; ! use IEEE.std_logic_arith.all; ! use IEEE.std_logic_signed."+"; ! use IEEE.math_real.all; ! use work.all; ! ! library work; ! use work.types_p.all; ! ! ! entity tb_Datapath is ! generic ( ! AnalogWidth : integer := 10; -- width of analog inputs ! DigitalWidth : integer := 32; -- width of digital inputs ! RAM_Width : integer := 72; -- width of data bus to RAM ! AverageWidth : integer := 36); -- width of averaged input (actually it is a sum) ! end tb_Datapath; ! ! architecture sim of tb_Datapath is ! signal Clk : std_logic := '0'; -- clock for all components ! signal Reset : std_logic := '0'; -- reset for all components ! signal I1 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel1 input ! signal I2 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel2 input ! signal I3 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel3 input ! signal I4 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel4 input ! signal Di : std_logic_vector(DigitalWidth-1 downto 0) := (others => '0'); -- digital inputs ! signal EnAD : std_logic := '0'; -- enable MAM-units at input ! signal ThAD : std_logic := '0'; -- allow inputs to pass MAM input units ! signal Latch : std_logic := '0'; -- latches hold values ! signal MAAM : MAAM_t; -- select Min/Avg1/Avg2/Max to be written to RAM or directed to MUX_uC ! signal RAMdir : std_logic := '0'; -- read/write RAM ! signal EnPP : std_logic := '0'; -- enable PP_Clk ! signal ThPP : std_logic := '0'; -- enable PP-units ! signal uCsel : std_logic_vector(3 downto 0) := (others => '0'); -- select 8 bit words -> output ! signal RAM : std_logic_vector(RAM_Width-1 downto 0); -- RAM values ! signal uC : std_logic_vector(7 downto 0); -- output to uC ! ! signal t_RAM : std_logic_vector(71 downto 0); -- varify RAM signal ! signal cs : integer := 0; -- for testing routine ! ! constant T2_clk : time := 6.26 ns; -- half period (80MHz) ! ! component Datapath ! generic ( ! AnalogWidth : integer; -- width of analog inputs ! DigitalWidth : integer; -- width of digital inputs ! RAM_Width : integer); -- width of data bus to RAM ! port ( ! CH1_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 1 ! CH2_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 2 ! CH3_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 3 ! CH4_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 4 ! Dig_i : in std_logic_vector(DigitalWidth-1 downto 0); -- digital input channels ! ! RAM_b : inout std_logic_vector(RAM_Width -1 downto 0); -- data path to memory ! ! uC_o : out std_logic_vector(7 downto 0); -- data bus to µC ! ! Clk : in std_logic; -- clock input ! Reset : in std_logic; -- reset input ! ! En_AD_i : in std_logic; -- enable MAMs at input side ! Through_AD_i : in std_logic; -- activate "Through_i" on MAMs at input side ! Latch_AD_i : in std_logic; -- activate Latches at input side ! MAAM_AD_i : in MAAM_t; -- select which group to be routed to RAM ! ! Through_PP_i : in std_logic; -- activate "Through_i" on MAMs at output side ! En_PP_i : in std_logic; -- enable PP_Clk unit ! MAAM_PP_i : in MAAM_t; -- select which group to be routet to the µC ! uC_Select_i : in std_logic_vector( 3 downto 0); -- select 8-bit packet from 72-bit data bus ! ! RAM_Dir_i : in std_logic); -- direction of RAM access (read/write) ! ! --constant AverageWidth : integer: = AverageWidth ; -- width of averaged input (actually it is a sum) ! end component; ! ! begin -- sim ! ! i_Datapath: Datapath ! generic map ( ! AnalogWidth => AnalogWidth, ! DigitalWidth => DigitalWidth, ! RAM_Width => RAM_Width) ! port map ( ! CH1_i => I1, ! CH2_i => I2, ! CH3_i => I3, ! CH4_i => I4, ! Dig_i => Di, ! RAM_b => RAM, ! uC_o => uC, ! Clk => Clk, ! Reset => Reset, ! En_AD_i => EnAD, ! Through_AD_i => ThAD, ! Latch_AD_i => Latch, ! MAAM_AD_i => MAAM , ! En_PP_i => EnPP, ! Through_PP_i => ThPP, ! MAAM_PP_i => MAAM , ! uC_Select_i => uCsel, ! RAM_Dir_i => RAMdir); ! ! -- purpose: generate Clk signal ! -- type : combinational ! -- inputs : ! -- outputs: Clk ! p_Clk: process ! begin -- process p_Clk ! Clk <= not Clk; ! wait for T2_clk; ! end process p_Clk; ! ! -- purpose: generate input signals ! -- type : combinational ! -- inputs : ! -- outputs: I1,I2,I3,I4,Di ! p_input: process ! variable count : integer := -50; -- count variable ! begin -- process p_input ! I1 <= conv_std_logic_vector(5*count,AnalogWidth); ! I3 <= conv_std_logic_vector(-5*count,AnalogWidth); ! I2 <= conv_std_logic_vector(count, AnalogWidth); ! I4 <= conv_std_logic_vector(-count, AnalogWidth); ! Di <= conv_std_logic_vector(count, DigitalWidth); ! count := count + 1; ! if count > 50 then ! count := 50; ! end if; ! wait for 10 ns; ! end process p_input; ! ! ! -- purpose: test datapath ! -- type : combinational ! -- inputs : ! -- outputs: ! p_Test: process ! ! begin -- process p_Test ! ! -- 1) test input -> RAM ! -- 1.1) trough at highest rate ! ! Reset <= '1'; ! wait for 20 ns; ! Reset <= '0'; ! wait for 20 ns; ! cs <= 1; ! EnAD <= '1'; ! ThAD <= '1'; ! Latch <= '1'; ! MAAM <= MAAM_Min; ! RAMdir <= '0'; ! wait for 2000 ns; ! ! -- 1.2) sampling at lower bitrate ! Reset <= '1'; ! wait for 20 ns; ! Reset <= '0'; ! wait for 20 ns; ! cs <= 2; ! RamDir <= '0'; ! EnAD <= '1'; ! ThAD <= '0'; ! Latch <= '1'; ! wait for 20*T2_Clk; ! Latch <= '0'; ! wait for 10*T2_Clk; ! MAAM <= MAAM_Min; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Max; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Avg1; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Avg2; ! wait for 2*T2_Clk; ! ! ! ! ! end process p_Test; ! ! -- purpose: varify output signals ! -- type : combinational ! -- inputs : RAM ! -- outputs: ! p_varify: process (RAM) ! begin -- process p_varify ! ! assert RAM = t_RAM report "signals do not match!" severity WARNING; ! ! end process p_varify; ! ! -- purpose: generating test signal t_RAM ! -- type : combinational ! -- inputs : Clk,Reset ! -- outputs: t_RAM ! p_genTest: process (Clk, Reset) ! variable help : std_logic_vector(71 downto 0); ! variable h_min, o_min : std_logic_vector(71 downto 0); ! variable h_max, o_max : std_logic_vector(71 downto 0); ! variable h_avg1,o_avg1 : std_logic_vector(71 downto 0); ! variable h_avg2,o_avg2 : std_logic_vector(71 downto 0); ! begin -- process p_genTest ! if Reset = '0' then -- asynchronous reset (active low) ! t_RAM <= (others => '0'); ! help := (others => '0'); ! h_min := (others => '0'); ! h_max := (others => '0'); ! h_avg1 := (others => '0'); ! h_avg2 := (others => '0'); ! o_min := (others => '0'); ! o_max := (others => '0'); ! o_avg1 := (others => '0'); ! o_avg2 := (others => '0'); ! ! elsif Clk'event and Clk = '1' then -- rising clock edge ! case cs is ! when 1 => help(71 downto 62) := I1; ! help(61 downto 52) := I2; ! help(51 downto 42) := I3; ! help(41 downto 32) := I4; ! help(31 downto 0) := Di; ! t_RAM <= help after 2*T2_Clk; ! when 2 => if I1 < h_min(71 downto 62) then ! h_min(71 downto 62) := I1; ! end if; ! if I2 < h_min(61 downto 52) then ! h_min(61 downto 52) := I2; ! end if; ! if I3 < h_min(51 downto 42) then ! h_min(51 downto 42) := I3; ! end if; ! if I4 < h_min(41 downto 32) then ! h_min(41 downto 32) := I4; ! end if; ! h_min(31 downto 0) := h_min(31 downto 0) and Di; ! ! if I1 > h_max(71 downto 62) then ! h_min(71 downto 62) := I1; ! end if; ! if I2 > h_max(61 downto 52) then ! h_min(61 downto 52) := I2; ! end if; ! if I3 > h_max(51 downto 42) then ! h_min(51 downto 42) := I3; ! end if; ! if I4 > h_max(41 downto 32) then ! h_min(41 downto 32) := I4; ! end if; ! h_max(31 downto 0) := h_max(31 downto 0) or Di; ! ! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I1; ! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I2; ! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I3; ! h_avg2(35 downto 0) := h_avg2(36 downto 0) + I4; ! ! if Latch='1' then ! o_min := h_min; ! o_max := h_max; ! o_avg1:= h_avg1; ! o_avg2:= h_avg2; ! end if; ! ! case MAAM is ! when MAAM_Min => t_RAM <= o_min; ! when MAAM_Max => t_RAM <= o_max; ! when MAAM_Avg1=> t_RAM <= o_avg1; ! when MAAM_Avg2=> t_RAM <= o_avg2; ! end case; ! ! when others => null; ! end case; ! ! end if; ! end process p_genTest; ! ! end sim; |
|
From: Gerald Z. <ri...@us...> - 2003-04-15 13:34:25
|
Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv9803/src
Modified Files:
MUX_AD_struc.vhd
Log Message:
Index: MUX_AD_struc.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MUX_AD_struc.vhd,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** MUX_AD_struc.vhd 15 Apr 2003 13:00:53 -0000 1.4
--- MUX_AD_struc.vhd 15 Apr 2003 13:34:20 -0000 1.5
***************
*** 31,41 ****
-------------------------------------------------------------------------------
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_arith.all;
-
- library work;
- use work.types_p.all;
-
architecture struc of MUX_AD is
--- 31,34 ----
***************
*** 68,73 ****
signal s_Avg2 : std_logic_vector(RAM_Width-1 downto 0);
signal s_Max : std_logic_vector(RAM_Width-1 downto 0);
- begin -- struc
i_Min : Join_MinMax
generic map (
--- 61,66 ----
signal s_Avg2 : std_logic_vector(RAM_Width-1 downto 0);
signal s_Max : std_logic_vector(RAM_Width-1 downto 0);
+ begin -- struc
i_Min : Join_MinMax
generic map (
|
|
From: Gerald Z. <ri...@us...> - 2003-04-15 13:01:24
|
Update of /cvsroot/dso/FPGA/msim In directory sc8-pr-cvs1:/tmp/cvs-serv22672/msim Modified Files: compile.tcl Log Message: MUX_AD_struc & Datapath_struc not compileable tb_Datapath not ready for test ---------------------------------------------------------------------- Index: compile.tcl =================================================================== RCS file: /cvsroot/dso/FPGA/msim/compile.tcl,v retrieving revision 1.12 retrieving revision 1.13 diff -C2 -d -r1.12 -r1.13 *** compile.tcl 1 Apr 2003 08:48:41 -0000 1.12 --- compile.tcl 15 Apr 2003 13:00:48 -0000 1.13 *************** *** 26,29 **** --- 26,30 ---- vcom -work work ../src/MUX_AD_.vhd vcom -work work ../src/MUX_RAM_.vhd + vcom -work work ../src/MUX_uC_.vhd vcom -work work ../src/Max_A_.vhd vcom -work work ../src/Min_A_.vhd *************** *** 43,48 **** vcom -work work ../src/MAM_D_P_struc.vhd vcom -work work ../src/MUX_4_N_rtl.vhd ! vcom -work work ../src/MUX_AD_rtl.vhd vcom -work work ../src/MUX_RAM_rtl.vhd vcom -work work ../src/Min_A_rtl.vhd vcom -work work ../src/Max_A_rtl.vhd --- 44,50 ---- vcom -work work ../src/MAM_D_P_struc.vhd vcom -work work ../src/MUX_4_N_rtl.vhd ! vcom -work work ../src/MUX_AD_struc.vhd vcom -work work ../src/MUX_RAM_rtl.vhd + vcom -work work ../src/MUX_uC_rtl.vhd vcom -work work ../src/Min_A_rtl.vhd vcom -work work ../src/Max_A_rtl.vhd |
|
From: Gerald Z. <ri...@us...> - 2003-04-15 13:01:05
|
Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv22672/src
Modified Files:
CountDown_struc.vhd Datapath_struc.vhd MUX_AD_.vhd
MUX_AD_struc.vhd
Log Message:
MUX_AD_struc & Datapath_struc not compileable
tb_Datapath not ready for test
----------------------------------------------------------------------
Index: CountDown_struc.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/CountDown_struc.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** CountDown_struc.vhd 3 Apr 2003 14:26:29 -0000 1.2
--- CountDown_struc.vhd 15 Apr 2003 13:00:50 -0000 1.3
***************
*** 29,34 ****
-------------------------------------------------------------------------------
! library work;
! use work.all;
library IEEE;
use IEEE.std_logic_arith.all;
--- 29,34 ----
-------------------------------------------------------------------------------
! --library work;
! --use work.all;
library IEEE;
use IEEE.std_logic_arith.all;
Index: Datapath_struc.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Datapath_struc.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** Datapath_struc.vhd 9 Apr 2003 11:10:48 -0000 1.2
--- Datapath_struc.vhd 15 Apr 2003 13:00:51 -0000 1.3
***************
*** 38,45 ****
architecture struc of Datapath is
!
component MAM_A is
! generic (AnalogWidth : integer := 10; -- data width for analog input/output
! AverageWidth : integer := 36); -- data width for Avg-output
port (In_i : in std_logic_vector(AnalogWidth-1 downto 0);
En_i : in std_logic;
--- 38,45 ----
architecture struc of Datapath is
!
component MAM_A is
! generic (AnalogWidth : integer; -- data width for analog input/output
! AverageWidth : integer); -- data width for Avg-output
port (In_i : in std_logic_vector(AnalogWidth-1 downto 0);
En_i : in std_logic;
Index: MUX_AD_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MUX_AD_.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** MUX_AD_.vhd 26 Feb 2003 10:10:09 -0000 1.3
--- MUX_AD_.vhd 15 Apr 2003 13:00:52 -0000 1.4
***************
*** 37,40 ****
--- 37,41 ----
library work;
use work.types_p.all;
+ use work.all;
entity MUX_AD is
Index: MUX_AD_struc.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MUX_AD_struc.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** MUX_AD_struc.vhd 5 Apr 2003 10:00:58 -0000 1.3
--- MUX_AD_struc.vhd 15 Apr 2003 13:00:53 -0000 1.4
***************
*** 1,162 ****
! -------------------------------------------------------------------------------
! --
! -- Author: Johann Glaser
! --
! -- Filename: MUX_AD_struc.vhd
! --
! -- Date of Creation: 26-02-2003
! --
! -- Description: Architecture for multiplexer of input signals. Selects the
! -- data from the inputs. Assembles the bit assumptions for storage
! -- in the RAM.
! --
! -------------------------------------------------------------------------------
! --
! -- Copyright (C) 2003 Johann Glaser
! --
! -- This program is free software; you can redistribute it and/or modify
! -- it under the terms of the GNU General Public License as published by
! -- the Free Software Foundation; either version 2 of the License, or
! -- (at your option) any later version.
! --
! -- This program is distributed in the hope that it will be useful,
! -- but WITHOUT ANY WARRANTY; without even the implied warranty of
! -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
! -- GNU General Public License for more details.
! --
! -- You should have received a copy of the GNU General Public License
! -- along with this program; if not, write to the Free Software
! -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
! --
! -------------------------------------------------------------------------------
!
! library ieee;
! use ieee.std_logic_1164.all;
! use ieee.std_logic_arith.all;
!
! library work;
! use work.types_p.all;
!
! architecture rtl of MUX_AD is
!
! component Join_Avg is
! generic (
! AverageWidth : Integer := 36; -- width of average data
! RAM_Width : Integer := 72); -- width of data bus to RAM
! port (
! Avg1_i : in std_logic_vector(AverageWidth-1 downto 0); -- data from first average channel
! Avg2_i : in std_logic_vector(AverageWidth-1 downto 0); -- data from second average channel
! Out_o : out std_logic_vector(RAM_Width-1 downto 0)); -- data path to RAM
! end component;
!
! component Join_MinMax is
! generic (
! AnalogWidth : Integer := 10; -- width of analog channels
! DigitalWidth : Integer := 32; -- width of digital input
! RAM_Width : Integer := 72); -- width of data bus to RAM
! port (
! Ch1_i : in std_logic_vector(AnalogWidth-1 downto 0); -- data from channel 1
! Ch2_i : in std_logic_vector(AnalogWidth-1 downto 0); -- data from channel 2
! Ch3_i : in std_logic_vector(AnalogWidth-1 downto 0); -- data from channel 3
! Ch4_i : in std_logic_vector(AnalogWidth-1 downto 0); -- data from channel 4
! Dig_i : in std_logic_vector(DigitalWidth-1 downto 0); -- data from digital inputs
! Out_o : out std_logic_vector(RAM_Width-1 downto 0)); -- data path to RAM
! end component;
!
! signal s_Min : std_logic_vector(RAM_Width-1 downto 0);
! signal s_Avg1 : std_logic_vector(RAM_Width-1 downto 0);
! signal s_Avg2 : std_logic_vector(RAM_Width-1 downto 0);
! signal s_Max : std_logic_vector(RAM_Width-1 downto 0);
! begin -- rtl
!
! i_Min : Join_MinMax
! generic map (
! AnalogWidth => AnalogWidth,
! DigitalWidth => DigitalWidth,
! RAM_Width => RAM_Width)
! port map (
! Ch1_i => Min1_i,
! Ch2_i => Min2_i,
! Ch3_i => Min3_i,
! Ch4_i => Min4_i,
! Dig_i => MinD_i,
! Out_o => s_Min);
!
! i_Avg1 : Join_Avg
! generic map (
! AverageWidth => AverageWidth,
! RAM_Width => RAM_Width)
! port map (
! Avg1_i => Avg1_i,
! Avg2_i => Avg2_i,
! Out_o => s_Avg1);
!
! i_Avg2 : Join_Avg
! generic map (
! AverageWidth => AverageWidth,
! RAM_Width => RAM_Width)
! port map (
! Avg1_i => Avg3_i,
! Avg2_i => Avg4_i,
! Out_o => s_Avg2);
!
! i_Max : Join_MinMax
! generic map (
! AnalogWidth => AnalogWidth,
! DigitalWidth => DigitalWidth,
! RAM_Width => RAM_Width)
! port map (
! Ch1_i => Max1_i,
! Ch2_i => Max2_i,
! Ch3_i => Max3_i,
! Ch4_i => Max4_i,
! Dig_i => MaxD_i,
! Out_o => s_Max);
!
! -- purpose: select which data packet is stored in the RAM word
! -- type : combinational
! -- inputs : MAAM_i,s_Min,s_Avg1,s_Avg2,s_Max
! -- outputs: RAM_o
! MUX: process (MAAM_i,s_Min,s_Avg1,s_Avg2,s_Max)
! begin -- process MUX
! case MAAM_i is
! when MAAM_Min => RAM_o <= s_Min;
! when MAAM_Avg1 => RAM_o <= s_Avg1;
! when MAAM_Avg2 => RAM_o <= s_Avg2;
! when others => RAM_o <= s_Max;
! end case;
! end process MUX;
!
!
! -- -- purpose: Select which data packet is stored in the RAM word
! -- -- type : combinational
! -- -- inputs : MAAM_i,Min1_i,Avg1_i,Max1_i,Min2_i,Avg2_i,Max2_i,
! -- -- Min3_i,Avg3_i,Max3_i,Min4_i,Avg4_i,Max4_i,MinD_i,MaxD_i
! -- -- outputs: RAM_o
! -- MUX: process (MAAM_i,
! -- Min1_i,Avg1_i,Max1_i,
! -- Min2_i,Avg2_i,Max2_i,
! -- Min3_i,Avg3_i,Max3_i,
! -- Min4_i,Avg4_i,Max4_i,
! -- MinD_i,MaxD_i)
! -- begin -- process MUX
! -- case MAAM_i is
! -- when MAAM_Min => RAM_o( AnalogWidth-1 downto 0) <= Min1_i;
! -- RAM_o( 2*AnalogWidth-1 downto AnalogWidth) <= Min2_i;
! -- RAM_o( 3*AnalogWidth-1 downto 2*AnalogWidth) <= Min3_i;
! -- RAM_o( 4*AnalogWidth-1 downto 3*AnalogWidth) <= Min4_i;
! -- RAM_o(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth) <= MinD_i;
! -- when MAAM_Avg1 => RAM_o( AverageWidth-1 downto 0) <= Avg1_i;
! -- RAM_o( 2*AverageWidth-1 downto AverageWidth) <= Avg2_i;
! -- when MAAM_Avg2 => RAM_o( AverageWidth-1 downto 0) <= Avg3_i;
! -- RAM_o( 2*AverageWidth-1 downto AverageWidth) <= Avg4_i;
! -- -- MAAM_Max:
! -- when others => RAM_o( AnalogWidth-1 downto 0) <= Max1_i;
! -- RAM_o( 2*AnalogWidth-1 downto AnalogWidth) <= Max2_i;
! -- RAM_o( 3*AnalogWidth-1 downto 2*AnalogWidth) <= Max3_i;
! -- RAM_o( 4*AnalogWidth-1 downto 3*AnalogWidth) <= Max4_i;
! -- RAM_o(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth) <= MaxD_i;
! -- end case;
! -- end process MUX;
!
! end rtl;
--- 1,162 ----
! -------------------------------------------------------------------------------
! --
! -- Author: Johann Glaser
! --
! -- Filename: MUX_AD_struc.vhd
! --
! -- Date of Creation: 26-02-2003
! --
! -- Description: Architecture for multiplexer of input signals. Selects the
! -- data from the inputs. Assembles the bit assumptions for storage
! -- in the RAM.
! --
! -------------------------------------------------------------------------------
! --
! -- Copyright (C) 2003 Johann Glaser
! --
! -- This program is free software; you can redistribute it and/or modify
! -- it under the terms of the GNU General Public License as published by
! -- the Free Software Foundation; either version 2 of the License, or
! -- (at your option) any later version.
! --
! -- This program is distributed in the hope that it will be useful,
! -- but WITHOUT ANY WARRANTY; without even the implied warranty of
! -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
! -- GNU General Public License for more details.
! --
! -- You should have received a copy of the GNU General Public License
! -- along with this program; if not, write to the Free Software
! -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
! --
! -------------------------------------------------------------------------------
!
! library ieee;
! use ieee.std_logic_1164.all;
! use ieee.std_logic_arith.all;
!
! library work;
! use work.types_p.all;
!
! architecture struc of MUX_AD is
!
! component Join_Avg is
! generic (
! AverageWidth : Integer; -- width of average data
! RAM_Width : Integer); -- width of data bus to RAM
! port (
! Avg1_i : in std_logic_vector(AverageWidth-1 downto 0); -- data from first average channel
! Avg2_i : in std_logic_vector(AverageWidth-1 downto 0); -- data from second average channel
! Out_o : out std_logic_vector(RAM_Width-1 downto 0)); -- data path to RAM
! end component;
!
! component Join_MinMax is
! generic (
! AnalogWidth : Integer; -- width of analog channels
! DigitalWidth : Integer; -- width of digital input
! RAM_Width : Integer); -- width of data bus to RAM
! port (
! Ch1_i : in std_logic_vector(AnalogWidth-1 downto 0); -- data from channel 1
! Ch2_i : in std_logic_vector(AnalogWidth-1 downto 0); -- data from channel 2
! Ch3_i : in std_logic_vector(AnalogWidth-1 downto 0); -- data from channel 3
! Ch4_i : in std_logic_vector(AnalogWidth-1 downto 0); -- data from channel 4
! Dig_i : in std_logic_vector(DigitalWidth-1 downto 0); -- data from digital inputs
! Out_o : out std_logic_vector(RAM_Width-1 downto 0)); -- data path to RAM
! end component;
!
! signal s_Min : std_logic_vector(RAM_Width-1 downto 0);
! signal s_Avg1 : std_logic_vector(RAM_Width-1 downto 0);
! signal s_Avg2 : std_logic_vector(RAM_Width-1 downto 0);
! signal s_Max : std_logic_vector(RAM_Width-1 downto 0);
! begin -- struc
!
! i_Min : Join_MinMax
! generic map (
! AnalogWidth => AnalogWidth,
! DigitalWidth => DigitalWidth,
! RAM_Width => RAM_Width)
! port map (
! Ch1_i => Min1_i,
! Ch2_i => Min2_i,
! Ch3_i => Min3_i,
! Ch4_i => Min4_i,
! Dig_i => MinD_i,
! Out_o => s_Min);
!
! i_Avg1 : Join_Avg
! generic map (
! AverageWidth => AverageWidth,
! RAM_Width => RAM_Width)
! port map (
! Avg1_i => Avg1_i,
! Avg2_i => Avg2_i,
! Out_o => s_Avg1);
!
! i_Avg2 : Join_Avg
! generic map (
! AverageWidth => AverageWidth,
! RAM_Width => RAM_Width)
! port map (
! Avg1_i => Avg3_i,
! Avg2_i => Avg4_i,
! Out_o => s_Avg2);
!
! i_Max : Join_MinMax
! generic map (
! AnalogWidth => AnalogWidth,
! DigitalWidth => DigitalWidth,
! RAM_Width => RAM_Width)
! port map (
! Ch1_i => Max1_i,
! Ch2_i => Max2_i,
! Ch3_i => Max3_i,
! Ch4_i => Max4_i,
! Dig_i => MaxD_i,
! Out_o => s_Max);
!
! -- purpose: select which data packet is stored in the RAM word
! -- type : combinational
! -- inputs : MAAM_i,s_Min,s_Avg1,s_Avg2,s_Max
! -- outputs: RAM_o
! MUX: process (MAAM_i,s_Min,s_Avg1,s_Avg2,s_Max)
! begin -- process MUX
! case MAAM_i is
! when MAAM_Min => RAM_o <= s_Min;
! when MAAM_Avg1 => RAM_o <= s_Avg1;
! when MAAM_Avg2 => RAM_o <= s_Avg2;
! when others => RAM_o <= s_Max;
! end case;
! end process MUX;
!
!
! -- -- purpose: Select which data packet is stored in the RAM word
! -- -- type : combinational
! -- -- inputs : MAAM_i,Min1_i,Avg1_i,Max1_i,Min2_i,Avg2_i,Max2_i,
! -- -- Min3_i,Avg3_i,Max3_i,Min4_i,Avg4_i,Max4_i,MinD_i,MaxD_i
! -- -- outputs: RAM_o
! -- MUX: process (MAAM_i,
! -- Min1_i,Avg1_i,Max1_i,
! -- Min2_i,Avg2_i,Max2_i,
! -- Min3_i,Avg3_i,Max3_i,
! -- Min4_i,Avg4_i,Max4_i,
! -- MinD_i,MaxD_i)
! -- begin -- process MUX
! -- case MAAM_i is
! -- when MAAM_Min => RAM_o( AnalogWidth-1 downto 0) <= Min1_i;
! -- RAM_o( 2*AnalogWidth-1 downto AnalogWidth) <= Min2_i;
! -- RAM_o( 3*AnalogWidth-1 downto 2*AnalogWidth) <= Min3_i;
! -- RAM_o( 4*AnalogWidth-1 downto 3*AnalogWidth) <= Min4_i;
! -- RAM_o(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth) <= MinD_i;
! -- when MAAM_Avg1 => RAM_o( AverageWidth-1 downto 0) <= Avg1_i;
! -- RAM_o( 2*AverageWidth-1 downto AverageWidth) <= Avg2_i;
! -- when MAAM_Avg2 => RAM_o( AverageWidth-1 downto 0) <= Avg3_i;
! -- RAM_o( 2*AverageWidth-1 downto AverageWidth) <= Avg4_i;
! -- -- MAAM_Max:
! -- when others => RAM_o( AnalogWidth-1 downto 0) <= Max1_i;
! -- RAM_o( 2*AnalogWidth-1 downto AnalogWidth) <= Max2_i;
! -- RAM_o( 3*AnalogWidth-1 downto 2*AnalogWidth) <= Max3_i;
! -- RAM_o( 4*AnalogWidth-1 downto 3*AnalogWidth) <= Max4_i;
! -- RAM_o(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth) <= MaxD_i;
! -- end case;
! -- end process MUX;
!
! end struc;
|
|
From: Gerald Z. <ri...@us...> - 2003-04-15 13:01:05
|
Update of /cvsroot/dso/FPGA/tb
In directory sc8-pr-cvs1:/tmp/cvs-serv22672/tb
Modified Files:
tb_Datapath.vhd
Log Message:
MUX_AD_struc & Datapath_struc not compileable
tb_Datapath not ready for test
----------------------------------------------------------------------
Index: tb_Datapath.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/tb/tb_Datapath.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** tb_Datapath.vhd 9 Apr 2003 11:10:49 -0000 1.1
--- tb_Datapath.vhd 15 Apr 2003 13:00:54 -0000 1.2
***************
*** 32,35 ****
--- 32,36 ----
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
+ use IEEE.math_real.all;
use work.all;
***************
*** 57,68 ****
signal ThAD : std_logic := '0'; -- allow inputs to pass MAM input units
signal Latch : std_logic := '0'; -- latches hold values
! signal MAAM_AD : MAAM_t; -- select Min/Avg1/Avg2/Max to be written to RAM
signal RAMdir : std_logic := '0'; -- read/write RAM
signal EnPP : std_logic := '0'; -- enable PP_Clk
- signal MAAM_PP : MAAM_t; -- select Min/Avg1/Avg2/Max to be directed to MUX_uC
signal ThPP : std_logic := '0'; -- enable PP-units
signal uCsel : std_logic_vector(3 downto 0) := (others => '0'); -- select 8 bit words -> output
signal RAM : std_logic_vector(RAM_Width-1 downto 0); -- RAM values
signal uC : std_logic_vector(7 downto 0); -- output to uC
component Datapath
--- 58,70 ----
signal ThAD : std_logic := '0'; -- allow inputs to pass MAM input units
signal Latch : std_logic := '0'; -- latches hold values
! signal MAAM : MAAM_t; -- select Min/Avg1/Avg2/Max to be written to RAM or directed to MUX_uC
signal RAMdir : std_logic := '0'; -- read/write RAM
signal EnPP : std_logic := '0'; -- enable PP_Clk
signal ThPP : std_logic := '0'; -- enable PP-units
signal uCsel : std_logic_vector(3 downto 0) := (others => '0'); -- select 8 bit words -> output
signal RAM : std_logic_vector(RAM_Width-1 downto 0); -- RAM values
signal uC : std_logic_vector(7 downto 0); -- output to uC
+
+ constant T2_clk : time := 6.26 ns; -- half period (80MHz)
component Datapath
***************
*** 97,101 ****
RAM_Dir_i : in std_logic); -- direction of RAM access (read/write)
! -- constant AverageWidth : integer: = AverageWidth ; -- width of averaged input (actually it is a sum)
end component;
--- 99,103 ----
RAM_Dir_i : in std_logic); -- direction of RAM access (read/write)
! --constant AverageWidth : integer: = AverageWidth ; -- width of averaged input (actually it is a sum)
end component;
***************
*** 120,127 ****
Through_AD_i => ThAD,
Latch_AD_i => Latch,
! MAAM_AD_i => MAAM_AD,
En_PP_i => EnPP,
Through_PP_i => ThPP,
! MAAM_PP_i => MAAM_PP,
uC_Select_i => uCsel,
RAM_Dir_i => RAMdir);
--- 122,129 ----
Through_AD_i => ThAD,
Latch_AD_i => Latch,
! MAAM_AD_i => MAAM ,
En_PP_i => EnPP,
Through_PP_i => ThPP,
! MAAM_PP_i => MAAM ,
uC_Select_i => uCsel,
RAM_Dir_i => RAMdir);
***************
*** 134,139 ****
begin -- process p_Clk
Clk <= not Clk;
! wait for 6.25 ns; -- 80 MHz clock eq T=12.5ns
end process p_Clk;
-------------------------------------------------------------------------------
--- 136,188 ----
begin -- process p_Clk
Clk <= not Clk;
! wait for T2_clk;
end process p_Clk;
+
+ -- purpose: generate input signals
+ -- type : combinational
+ -- inputs :
+ -- outputs: I1,I2,I3,I4,Di
+ p_input: process
+ variable count : integer := -50; -- count variable
+ begin -- process p_input
+ I1 <= conv_std_logic_vector(count/10,AnalogWidth);
+ I3 <= I1;
+ I2 <= conv_std_logic_vector(count, AnalogWidth);
+ I4 <= I2;
+ Di <= conv_std_logic_vector(count, DigitalWidth);
+ count := count + 1;
+ if count > 50 then
+ count := 50;
+ end if;
+ wait for 10 ns;
+ end process p_input;
+
+ -- 1) test input -> RAM
+ -- 1.1) trough at highest rate
+
+ -- purpose: test datapath
+ -- type : combinational
+ -- inputs :
+ -- outputs:
+ p_Test: process
+
+ begin -- process p_Test
+ Reset <= '1';
+ wait for 20 ns;
+ Reset <= '0';
+ wait for 20 ns;
+ EnAD <= '1';
+ ThAD <= '1';
+ Latch <= '1';
+ MAAM <= MAAM_Min;
+ RAMdir <= '0';
+ wait for 5000 ns;
+
+ end process p_Test;
+
+
+
+
+
-------------------------------------------------------------------------------
|
|
From: Johann G. <han...@us...> - 2003-04-09 11:43:58
|
Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv18464/src
Modified Files:
MUX_N_1_.vhd MUX_N_1_rtl.vhd PP_Clk_rtl.vhd
Log Message:
Updated TODO.
Added PP_Clk and MUX_N_1 implementations to Synplify project.
Changed Ndata and Nsel to DataWidth and SelectWidth for MUX_N_1.
Added En_i to PP_Clk's sensitivity list.
Index: MUX_N_1_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MUX_N_1_.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** MUX_N_1_.vhd 9 Apr 2003 09:50:19 -0000 1.2
--- MUX_N_1_.vhd 9 Apr 2003 11:43:54 -0000 1.3
***************
*** 39,49 ****
generic (
! Ndata : Integer := 13; -- # of inputs to mux
! Nsel : Integer := 4); -- # of select lines (= next greater intval(log2(Ndata)))
port (
! In_i : in std_logic_vector(Ndata-1 downto 0); -- input data paths
Out_o : out std_logic; -- output
! Sel_i : in std_logic_vector(NSel downto 0)); -- select the input data path
end MUX_N_1;
--- 39,49 ----
generic (
! DataWidth : Integer := 13; -- # of inputs to mux
! SelectWidth : Integer := 4); -- # of select lines (= next greater intval(log2(DataWidth)))
port (
! In_i : in std_logic_vector(DataWidth-1 downto 0); -- input data paths
Out_o : out std_logic; -- output
! Sel_i : in std_logic_vector(SelectWidth-1 downto 0)); -- select the input data path
end MUX_N_1;
Index: MUX_N_1_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MUX_N_1_rtl.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** MUX_N_1_rtl.vhd 9 Apr 2003 11:10:49 -0000 1.2
--- MUX_N_1_rtl.vhd 9 Apr 2003 11:43:54 -0000 1.3
***************
*** 43,47 ****
p_MUX_N_1: process (Sel_i, In_i)
begin -- process p_MUX_N_1
! if conv_integer(Sel_i) > (Ndata-1) then
Out_o <= 'X';
else
--- 43,47 ----
p_MUX_N_1: process (Sel_i, In_i)
begin -- process p_MUX_N_1
! if conv_integer(Sel_i) > (DataWidth-1) then
Out_o <= 'X';
else
Index: PP_Clk_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/PP_Clk_rtl.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** PP_Clk_rtl.vhd 9 Apr 2003 11:10:49 -0000 1.3
--- PP_Clk_rtl.vhd 9 Apr 2003 11:43:54 -0000 1.4
***************
*** 43,49 ****
-- purpose: select one out of the 2 Clock enable signals out of MAAM_i
-- type : combinational
! -- inputs : MAAM_i
-- outputs: EnMin_o, EnAvg1_o, EnAvg2_o, EnMax_o
! MUX: process (MAAM_i)
begin -- process MUX
if En_i = '1' then
--- 43,49 ----
-- purpose: select one out of the 2 Clock enable signals out of MAAM_i
-- type : combinational
! -- inputs : MAAM_i,En_i
-- outputs: EnMin_o, EnAvg1_o, EnAvg2_o, EnMax_o
! MUX: process (MAAM_i,En_i)
begin -- process MUX
if En_i = '1' then
|
|
From: Johann G. <han...@us...> - 2003-04-09 11:43:58
|
Update of /cvsroot/dso/FPGA
In directory sc8-pr-cvs1:/tmp/cvs-serv18464
Modified Files:
TODO
Log Message:
Updated TODO.
Added PP_Clk and MUX_N_1 implementations to Synplify project.
Changed Ndata and Nsel to DataWidth and SelectWidth for MUX_N_1.
Added En_i to PP_Clk's sensitivity list.
Index: TODO
===================================================================
RCS file: /cvsroot/dso/FPGA/TODO,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** TODO 4 Apr 2003 09:32:27 -0000 1.5
--- TODO 9 Apr 2003 11:43:54 -0000 1.6
***************
*** 1,5 ****
- Architectures for DSO, Control, Kernel and Trigger
! - Architecture and Entity for Datapath
- tb_MAM_A.vhd: line 84: "1=1" -- can be written as "(true)"
- tb_Avg_A.vhd: clock and reset are modelled awkwardly
--- 1,5 ----
- Architectures for DSO, Control, Kernel and Trigger
! - Testbench for Datapath
- tb_MAM_A.vhd: line 84: "1=1" -- can be written as "(true)"
- tb_Avg_A.vhd: clock and reset are modelled awkwardly
***************
*** 10,15 ****
- pinout
- screenshot of layout
- - examine all entities and draw new schematic symbols
- adjust all testbenches to the changed architectures
- use "En" and "Through" signals in testbenches
- update compile.tcl for the new files
--- 10,19 ----
- pinout
- screenshot of layout
- adjust all testbenches to the changed architectures
- use "En" and "Through" signals in testbenches
- update compile.tcl for the new files
+ - make drawings for entities: Join_MinMax, Join_Avg, MUX_4_N, DownCounter,
+ Reg_N_Load_8, CountDown, UpCounter, Kernel, MUX_N_1
+ - make drawings for structural architectures: DSO, Control,
+ Trigger, MAM_D, MAM_D_P, Join_MinMax, Join_Avg
+ - make drawings for the RTL architectures: (use from Synplify or so)
|
|
From: Johann G. <han...@us...> - 2003-04-09 11:43:57
|
Update of /cvsroot/dso/FPGA/Synplify In directory sc8-pr-cvs1:/tmp/cvs-serv18464/Synplify Modified Files: project.prd project.prj Log Message: Updated TODO. Added PP_Clk and MUX_N_1 implementations to Synplify project. Changed Ndata and Nsel to DataWidth and SelectWidth for MUX_N_1. Added En_i to PP_Clk's sensitivity list. Index: project.prd =================================================================== RCS file: /cvsroot/dso/FPGA/Synplify/project.prd,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** project.prd 8 Apr 2003 13:25:08 -0000 1.2 --- project.prd 9 Apr 2003 11:43:54 -0000 1.3 *************** *** 2,6 **** #-- Version 7.0.3 #-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prd ! #-- Written on Sat Apr 5 18:08:02 2003 # --- 2,6 ---- #-- Version 7.0.3 #-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prd ! #-- Written on Wed Apr 9 13:41:37 2003 # Index: project.prj =================================================================== RCS file: /cvsroot/dso/FPGA/Synplify/project.prj,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** project.prj 8 Apr 2003 13:25:09 -0000 1.2 --- project.prj 9 Apr 2003 11:43:54 -0000 1.3 *************** *** 2,6 **** #-- Version 7.0.3 #-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prj ! #-- Written on Sat Apr 5 18:08:02 2003 --- 2,6 ---- #-- Version 7.0.3 #-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prj ! #-- Written on Wed Apr 9 13:41:37 2003 *************** *** 36,40 **** add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_4_N_rtl.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_AD_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_AD_rtl.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/DEMUX_PP_.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/DEMUX_PP_rtl.vhd" --- 36,40 ---- add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_4_N_rtl.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_AD_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_AD_struc.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/DEMUX_PP_.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/DEMUX_PP_rtl.vhd" *************** *** 55,58 **** --- 55,60 ---- add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Datapath_.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Datapath_struc.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_N_1_.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_N_1_rtl.vhd" #reporting options *************** *** 75,82 **** #map options ! set_option -frequency 0.000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 set_option -retiming 0 --- 77,85 ---- #map options ! set_option -frequency 0,000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 + set_option -modular 0 set_option -retiming 0 *************** *** 108,115 **** #map options ! set_option -frequency 0.000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 set_option -retiming 0 --- 111,119 ---- #map options ! set_option -frequency 0,000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 + set_option -modular 0 set_option -retiming 0 *************** *** 141,148 **** #map options ! set_option -frequency 0.000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 set_option -retiming 0 --- 145,153 ---- #map options ! set_option -frequency 0,000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 + set_option -modular 0 set_option -retiming 0 *************** *** 174,181 **** #map options ! set_option -frequency 0.000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 set_option -retiming 0 --- 179,187 ---- #map options ! set_option -frequency 0,000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 + set_option -modular 0 set_option -retiming 0 *************** *** 207,214 **** #map options ! set_option -frequency 0.000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 set_option -retiming 0 --- 213,221 ---- #map options ! set_option -frequency 0,000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 + set_option -modular 0 set_option -retiming 0 *************** *** 240,247 **** #map options ! set_option -frequency 0.000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 set_option -retiming 0 --- 247,255 ---- #map options ! set_option -frequency 0,000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 + set_option -modular 0 set_option -retiming 0 *************** *** 273,280 **** #map options ! set_option -frequency 0.000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 set_option -retiming 0 --- 281,289 ---- #map options ! set_option -frequency 0,000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 + set_option -modular 0 set_option -retiming 0 *************** *** 306,313 **** #map options ! set_option -frequency 0.000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 set_option -retiming 0 --- 315,323 ---- #map options ! set_option -frequency 0,000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 + set_option -modular 0 set_option -retiming 0 *************** *** 339,346 **** #map options ! set_option -frequency 0.000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 set_option -retiming 0 --- 349,357 ---- #map options ! set_option -frequency 0,000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 + set_option -modular 0 set_option -retiming 0 *************** *** 372,379 **** #map options ! set_option -frequency 0.000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 set_option -retiming 0 --- 383,391 ---- #map options ! set_option -frequency 0,000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 + set_option -modular 0 set_option -retiming 0 *************** *** 405,412 **** #map options ! set_option -frequency 100.000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 set_option -retiming 0 --- 417,425 ---- #map options ! set_option -frequency 100,000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 + set_option -modular 0 set_option -retiming 0 *************** *** 438,445 **** #map options ! set_option -frequency 80.000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 set_option -retiming 0 --- 451,459 ---- #map options ! set_option -frequency 80,000 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 0 + set_option -modular 0 set_option -retiming 0 *************** *** 453,455 **** #set result format/file last project -result_file "Datapath/rev_1.edf" ! impl -active "Datapath" --- 467,537 ---- #set result format/file last project -result_file "Datapath/rev_1.edf" ! ! ! #implementation: "MUX_N_1" ! impl -add MUX_N_1 ! ! #device options ! set_option -technology VIRTEX ! set_option -part XCV200 ! set_option -package PQ240 ! set_option -speed_grade -6 ! ! #compilation/mapping options ! set_option -default_enum_encoding onehot ! set_option -symbolic_fsm_compiler 1 ! set_option -resource_sharing 1 ! set_option -top_module "MUX_N_1" ! ! #map options ! set_option -frequency 80,000 ! set_option -fanout_limit 100 ! set_option -disable_io_insertion 0 ! set_option -pipe 0 ! set_option -modular 0 ! set_option -retiming 0 ! ! #simulation options ! set_option -write_verilog 0 ! set_option -write_vhdl 0 ! ! #automatic place and route (vendor) options ! set_option -write_apr_constraint 1 ! ! #set result format/file last ! project -result_file "MUX_N_1/rev_1.edf" ! ! ! #implementation: "PP_Clk" ! impl -add PP_Clk ! ! #device options ! set_option -technology VIRTEX ! set_option -part XCV200 ! set_option -package PQ240 ! set_option -speed_grade -6 ! ! #compilation/mapping options ! set_option -default_enum_encoding onehot ! set_option -symbolic_fsm_compiler 1 ! set_option -resource_sharing 1 ! set_option -top_module "PP_Clk" ! ! #map options ! set_option -frequency 80,000 ! set_option -fanout_limit 100 ! set_option -disable_io_insertion 0 ! set_option -pipe 0 ! set_option -modular 0 ! set_option -retiming 0 ! ! #simulation options ! set_option -write_verilog 0 ! set_option -write_vhdl 0 ! ! #automatic place and route (vendor) options ! set_option -write_apr_constraint 1 ! ! #set result format/file last ! project -result_file "PP_Clk/rev_1.edf" ! impl -active "PP_Clk" |
|
From: Gerald Z. <ri...@us...> - 2003-04-09 11:10:53
|
Update of /cvsroot/dso/FPGA/tb
In directory sc8-pr-cvs1:/tmp/cvs-serv2396/tb
Added Files:
tb_Datapath.vhd
Log Message:
tb_Datapath in progress ...
-----------------------------
Datapath_struc causes error during compiling(??) can't find anyerror!
Hansi, please try to find out what happend! :-)
-----------------------------------------------
few changes in Datapath_ & Datapath_struc: En_PP_i signal added
-------------------------------------------------------------
--- NEW FILE: tb_Datapath.vhd ---
-------------------------------------------------------------------------------
--
-- Author: Gerald Zach
--
-- Filename: tb_CountDown.vhd
--
-- Date of Creation: 09-04-2003
--
-- Description: Testbench for Datapath
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2003 Gerald Zach
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.all;
library work;
use work.types_p.all;
entity tb_Datapath is
generic (
AnalogWidth : integer := 10; -- width of analog inputs
DigitalWidth : integer := 32; -- width of digital inputs
RAM_Width : integer := 72; -- width of data bus to RAM
AverageWidth : integer := 36); -- width of averaged input (actually it is a sum)
end tb_Datapath;
architecture sim of tb_Datapath is
signal Clk : std_logic := '0'; -- clock for all components
signal Reset : std_logic := '0'; -- reset for all components
signal I1 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel1 input
signal I2 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel2 input
signal I3 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel3 input
signal I4 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel4 input
signal Di : std_logic_vector(DigitalWidth-1 downto 0) := (others => '0'); -- digital inputs
signal EnAD : std_logic := '0'; -- enable MAM-units at input
signal ThAD : std_logic := '0'; -- allow inputs to pass MAM input units
signal Latch : std_logic := '0'; -- latches hold values
signal MAAM_AD : MAAM_t; -- select Min/Avg1/Avg2/Max to be written to RAM
signal RAMdir : std_logic := '0'; -- read/write RAM
signal EnPP : std_logic := '0'; -- enable PP_Clk
signal MAAM_PP : MAAM_t; -- select Min/Avg1/Avg2/Max to be directed to MUX_uC
signal ThPP : std_logic := '0'; -- enable PP-units
signal uCsel : std_logic_vector(3 downto 0) := (others => '0'); -- select 8 bit words -> output
signal RAM : std_logic_vector(RAM_Width-1 downto 0); -- RAM values
signal uC : std_logic_vector(7 downto 0); -- output to uC
component Datapath
generic (
AnalogWidth : integer; -- width of analog inputs
DigitalWidth : integer; -- width of digital inputs
RAM_Width : integer); -- width of data bus to RAM
port (
CH1_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 1
CH2_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 2
CH3_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 3
CH4_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 4
Dig_i : in std_logic_vector(DigitalWidth-1 downto 0); -- digital input channels
RAM_b : inout std_logic_vector(RAM_Width -1 downto 0); -- data path to memory
uC_o : out std_logic_vector(7 downto 0); -- data bus to µC
Clk : in std_logic; -- clock input
Reset : in std_logic; -- reset input
En_AD_i : in std_logic; -- enable MAMs at input side
Through_AD_i : in std_logic; -- activate "Through_i" on MAMs at input side
Latch_AD_i : in std_logic; -- activate Latches at input side
MAAM_AD_i : in MAAM_t; -- select which group to be routed to RAM
Through_PP_i : in std_logic; -- activate "Through_i" on MAMs at output side
En_PP_i : in std_logic; -- enable PP_Clk unit
MAAM_PP_i : in MAAM_t; -- select which group to be routet to the µC
uC_Select_i : in std_logic_vector( 3 downto 0); -- select 8-bit packet from 72-bit data bus
RAM_Dir_i : in std_logic); -- direction of RAM access (read/write)
-- constant AverageWidth : integer: = AverageWidth ; -- width of averaged input (actually it is a sum)
end component;
begin -- sim
i_Datapath: Datapath
generic map (
AnalogWidth => AnalogWidth,
DigitalWidth => DigitalWidth,
RAM_Width => RAM_Width)
port map (
CH1_i => I1,
CH2_i => I2,
CH3_i => I3,
CH4_i => I4,
Dig_i => Di,
RAM_b => RAM,
uC_o => uC,
Clk => Clk,
Reset => Reset,
En_AD_i => EnAD,
Through_AD_i => ThAD,
Latch_AD_i => Latch,
MAAM_AD_i => MAAM_AD,
En_PP_i => EnPP,
Through_PP_i => ThPP,
MAAM_PP_i => MAAM_PP,
uC_Select_i => uCsel,
RAM_Dir_i => RAMdir);
-- purpose: generate Clk signal
-- type : combinational
-- inputs :
-- outputs: Clk
p_Clk: process
begin -- process p_Clk
Clk <= not Clk;
wait for 6.25 ns; -- 80 MHz clock eq T=12.5ns
end process p_Clk;
-------------------------------------------------------------------------------
--
-- insert further processes for testing *Datapath*
--
-------------------------------------------------------------------------------
end sim;
|
|
From: Gerald Z. <ri...@us...> - 2003-04-09 11:10:53
|
Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv2396/src
Modified Files:
Datapath_.vhd Datapath_struc.vhd MUX_N_1_rtl.vhd PP_Clk_.vhd
PP_Clk_rtl.vhd
Log Message:
tb_Datapath in progress ...
-----------------------------
Datapath_struc causes error during compiling(??) can't find anyerror!
Hansi, please try to find out what happend! :-)
-----------------------------------------------
few changes in Datapath_ & Datapath_struc: En_PP_i signal added
-------------------------------------------------------------
Index: Datapath_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Datapath_.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** Datapath_.vhd 8 Apr 2003 13:25:15 -0000 1.1
--- Datapath_.vhd 9 Apr 2003 11:10:48 -0000 1.2
***************
*** 61,64 ****
--- 61,65 ----
Through_PP_i : in std_logic; -- activate "Through_i" on MAMs at output side
+ En_PP_i : in std_logic; -- enable PP_Clk unit
MAAM_PP_i : in MAAM_t; -- select which group to be routet to the µC
uC_Select_i : in std_logic_vector( 3 downto 0); -- select 8-bit packet from 72-bit data bus
Index: Datapath_struc.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Datapath_struc.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** Datapath_struc.vhd 8 Apr 2003 13:25:16 -0000 1.1
--- Datapath_struc.vhd 9 Apr 2003 11:10:48 -0000 1.2
***************
*** 186,189 ****
--- 186,190 ----
port (
MAAM_i : in MAAM_t; -- select input
+ En_i : in std_logic; -- enable PP_Clk unit
EnMin_o : out std_logic; -- selects the minima
EnAvg1_o : out std_logic; -- selects the first averages
***************
*** 545,548 ****
--- 546,550 ----
port map (
MAAM_i => MAAM_PP_i,
+ En_i => En_PP_i,
EnMin_o => EnMin,
EnAvg1_o => EnAvg1,
Index: MUX_N_1_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MUX_N_1_rtl.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** MUX_N_1_rtl.vhd 9 Apr 2003 09:50:20 -0000 1.1
--- MUX_N_1_rtl.vhd 9 Apr 2003 11:10:49 -0000 1.2
***************
*** 44,48 ****
begin -- process p_MUX_N_1
if conv_integer(Sel_i) > (Ndata-1) then
! Out_o <= '0';
else
Out_o <= In_i(conv_integer(Sel_i));
--- 44,48 ----
begin -- process p_MUX_N_1
if conv_integer(Sel_i) > (Ndata-1) then
! Out_o <= 'X';
else
Out_o <= In_i(conv_integer(Sel_i));
Index: PP_Clk_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/PP_Clk_.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** PP_Clk_.vhd 9 Apr 2003 09:50:20 -0000 1.2
--- PP_Clk_.vhd 9 Apr 2003 11:10:49 -0000 1.3
***************
*** 40,49 ****
port (
! MAAM_i : in MAAM_t; -- select input
! En_PP_i : in std_logic; -- enables/disables unit PP_Clk
! EnMin_o : out std_logic; -- selects the minima
! EnAvg1_o : out std_logic; -- selects the first averages
! EnAvg2_o : out std_logic; -- selects the second averages
! EnMax_o : out std_logic); -- selects the maxima
end PP_Clk;
--- 40,49 ----
port (
! MAAM_i : in MAAM_t; -- select input
! En_i : in std_logic; -- enables/disables unit PP_Clk
! EnMin_o : out std_logic; -- selects the minima
! EnAvg1_o : out std_logic; -- selects the first averages
! EnAvg2_o : out std_logic; -- selects the second averages
! EnMax_o : out std_logic); -- selects the maxima
end PP_Clk;
Index: PP_Clk_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/PP_Clk_rtl.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** PP_Clk_rtl.vhd 9 Apr 2003 09:50:20 -0000 1.2
--- PP_Clk_rtl.vhd 9 Apr 2003 11:10:49 -0000 1.3
***************
*** 47,51 ****
MUX: process (MAAM_i)
begin -- process MUX
! if En_PP_i = '1' then
case MAAM_i is
when MAAM_Min => EnMin_o <= '1'; EnAvg1_o <= '0'; EnAvg2_o <= '0'; EnMax_o <= '0';
--- 47,51 ----
MUX: process (MAAM_i)
begin -- process MUX
! if En_i = '1' then
case MAAM_i is
when MAAM_Min => EnMin_o <= '1'; EnAvg1_o <= '0'; EnAvg2_o <= '0'; EnMax_o <= '0';
|
|
From: Gerald Z. <ri...@us...> - 2003-04-09 09:50:23
|
Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv1076
Modified Files:
MUX_N_1_.vhd PP_Clk_.vhd PP_Clk_rtl.vhd
Added Files:
MUX_N_1_rtl.vhd
Log Message:
enable input added to PP_Clk
MUX_N_1 rtl-design added
--- NEW FILE: MUX_N_1_rtl.vhd ---
-------------------------------------------------------------------------------
--
-- Author: Gerald Zach
--
-- Filename: MUX_N_1.vhd
--
-- Date of Creation: 09-04-2003
--
-- Description: multiplexes 1 out of N datapaths - rtl design
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2003 Gerald Zach
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
architecture rtl of MUX_N_1 is
begin -- rtl
-- purpose: multiplex N input paths to 1 output
-- type : combinational
-- inputs : Sel_i, In_i
-- outputs: Out_o
p_MUX_N_1: process (Sel_i, In_i)
begin -- process p_MUX_N_1
if conv_integer(Sel_i) > (Ndata-1) then
Out_o <= '0';
else
Out_o <= In_i(conv_integer(Sel_i));
end if;
end process p_MUX_N_1;
end rtl;
Index: MUX_N_1_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MUX_N_1_.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** MUX_N_1_.vhd 27 Feb 2003 13:40:34 -0000 1.1
--- MUX_N_1_.vhd 9 Apr 2003 09:50:19 -0000 1.2
***************
*** 1,15 ****
-------------------------------------------------------------------------------
--
! -- Author: Sobhi Maher
--
-- Filename: MUX_N_1.vhd
--
! -- Date of Creation: 25-02-2003
--
! -- Description: multiplexes 1 out of 4 72 bit wide data paths
--
-------------------------------------------------------------------------------
--
! -- Copyright (C) 2003 Sobhi Maher
--
-- This program is free software; you can redistribute it and/or modify
--- 1,15 ----
-------------------------------------------------------------------------------
--
! -- Author: Gerald Zach
--
-- Filename: MUX_N_1.vhd
--
! -- Date of Creation: 09-04-2003
--
! -- Description: multiplexes 1 out of N datapaths
--
-------------------------------------------------------------------------------
--
! -- Copyright (C) 2003 Gerald Zach
--
-- This program is free software; you can redistribute it and/or modify
***************
*** 39,50 ****
generic (
! Width : Integer := 72); -- data path width
!
port (
!
! In_i : in std_logic_vector(Width-1 downto 0); -- input 1
!
! Out_o : out std_logic_vector(Width-1 downto 0); -- output
! Select_i : in std_logic_vector(n downto 0)); -- select the input data path
end MUX_N_1;
--- 39,49 ----
generic (
! Ndata : Integer := 13; -- # of inputs to mux
! Nsel : Integer := 4); -- # of select lines (= next greater intval(log2(Ndata)))
port (
! In_i : in std_logic_vector(Ndata-1 downto 0); -- input data paths
! Out_o : out std_logic; -- output
!
! Sel_i : in std_logic_vector(NSel downto 0)); -- select the input data path
end MUX_N_1;
Index: PP_Clk_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/PP_Clk_.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** PP_Clk_.vhd 4 Apr 2003 07:43:15 -0000 1.1
--- PP_Clk_.vhd 9 Apr 2003 09:50:20 -0000 1.2
***************
*** 41,48 ****
port (
MAAM_i : in MAAM_t; -- select input
EnMin_o : out std_logic; -- selects the minima
EnAvg1_o : out std_logic; -- selects the first averages
EnAvg2_o : out std_logic; -- selects the second averages
! EnMax_o : out std_logic); -- selects the maxima
end PP_Clk;
--- 41,49 ----
port (
MAAM_i : in MAAM_t; -- select input
+ En_PP_i : in std_logic; -- enables/disables unit PP_Clk
EnMin_o : out std_logic; -- selects the minima
EnAvg1_o : out std_logic; -- selects the first averages
EnAvg2_o : out std_logic; -- selects the second averages
! EnMax_o : out std_logic); -- selects the maxima
end PP_Clk;
Index: PP_Clk_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/PP_Clk_rtl.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** PP_Clk_rtl.vhd 4 Apr 2003 07:43:15 -0000 1.1
--- PP_Clk_rtl.vhd 9 Apr 2003 09:50:20 -0000 1.2
***************
*** 47,56 ****
MUX: process (MAAM_i)
begin -- process MUX
! case MAAM_i is
! when MAAM_Min => EnMin_o <= '1'; EnAvg1_o <= '0'; EnAvg2_o <= '0'; EnMax_o <= '0';
! when MAAM_Avg1 => EnMin_o <= '0'; EnAvg1_o <= '1'; EnAvg2_o <= '0'; EnMax_o <= '0';
! when MAAM_Avg2 => EnMin_o <= '0'; EnAvg1_o <= '0'; EnAvg2_o <= '1'; EnMax_o <= '0';
! when others => EnMin_o <= '0'; EnAvg1_o <= '0'; EnAvg2_o <= '0'; EnMax_o <= '1'; -- MAAM_Max
! end case;
end process MUX;
--- 47,63 ----
MUX: process (MAAM_i)
begin -- process MUX
! if En_PP_i = '1' then
! case MAAM_i is
! when MAAM_Min => EnMin_o <= '1'; EnAvg1_o <= '0'; EnAvg2_o <= '0'; EnMax_o <= '0';
! when MAAM_Avg1 => EnMin_o <= '0'; EnAvg1_o <= '1'; EnAvg2_o <= '0'; EnMax_o <= '0';
! when MAAM_Avg2 => EnMin_o <= '0'; EnAvg1_o <= '0'; EnAvg2_o <= '1'; EnMax_o <= '0';
! when others => EnMin_o <= '0'; EnAvg1_o <= '0'; EnAvg2_o <= '0'; EnMax_o <= '1'; -- MAAM_Max
! end case;
! else
! EnMin_o <= '0';
! EnAvg1_o <= '0';
! EnAvg2_o <= '0';
! EnMax_o <= '0';
! end if;
end process MUX;
|
Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv1806/src
Modified Files:
Avg_A_.vhd Avg_A_rtl.vhd Latch_D_.vhd MAM_A_.vhd MAM_A_P_.vhd
MAM_A_P_struc.vhd MAM_A_struc.vhd MAM_D_.vhd MAM_D_P_.vhd
MAM_D_P_struc.vhd MAM_D_struc.vhd Max_A_.vhd Max_A_rtl.vhd
Max_D_.vhd Max_D_rtl.vhd Min_A_.vhd Min_A_rtl.vhd Min_D_.vhd
Min_D_rtl.vhd Trigger_.vhd
Added Files:
Datapath_.vhd Datapath_struc.vhd
Log Message:
Renamed signals "Through" to "Through_i" and "En" to "En_i".
Added entity and architecture of Datapath.
--- NEW FILE: Datapath_.vhd ---
-------------------------------------------------------------------------------
--
-- Author: Johann Glaser
--
-- Filename: Datapath_.vhd
--
-- Date of Creation: 04-05-2003
--
-- Description: data path
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2003 Johann Glaser
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.types_p.all;
entity Datapath is
generic (
AnalogWidth : integer := 10; -- width of analog inputs
DigitalWidth : integer := 32; -- width of digital inputs
RAM_Width : integer := 72); -- width of data bus to RAM
port (
CH1_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 1
CH2_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 2
CH3_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 3
CH4_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 4
Dig_i : in std_logic_vector(DigitalWidth-1 downto 0); -- digital input channels
RAM_b : inout std_logic_vector(RAM_Width -1 downto 0); -- data path to memory
uC_o : out std_logic_vector(7 downto 0); -- data bus to µC
Clk : in std_logic; -- clock input
Reset : in std_logic; -- reset input
En_AD_i : in std_logic; -- enable MAMs at input side
Through_AD_i : in std_logic; -- activate "Through_i" on MAMs at input side
Latch_AD_i : in std_logic; -- activate Latches at input side
MAAM_AD_i : in MAAM_t; -- select which group to be routed to RAM
Through_PP_i : in std_logic; -- activate "Through_i" on MAMs at output side
MAAM_PP_i : in MAAM_t; -- select which group to be routet to the µC
uC_Select_i : in std_logic_vector( 3 downto 0); -- select 8-bit packet from 72-bit data bus
RAM_Dir_i : in std_logic); -- direction of RAM access (read/write)
constant AverageWidth : integer := 36; -- width of averaged input (actually it is a sum)
end Datapath;
--- NEW FILE: Datapath_struc.vhd ---
-------------------------------------------------------------------------------
--
-- Author: Johann Glaser
--
-- Filename: Datapath_struc.vhd
--
-- Date of Creation: 04-05-2003
--
-- Description: data path
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2003 Johann Glaser
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.types_p.all;
architecture struc of Datapath is
component MAM_A is
generic (AnalogWidth : integer := 10; -- data width for analog input/output
AverageWidth : integer := 36); -- data width for Avg-output
port (In_i : in std_logic_vector(AnalogWidth-1 downto 0);
En_i : in std_logic;
Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
Clk : in std_logic;
Reset : in std_logic;
Min_o : out std_logic_vector(AnalogWidth -1 downto 0);
Avg_o : out std_logic_vector(AverageWidth-1 downto 0);
Max_o : out std_logic_vector(AnalogWidth -1 downto 0));
end component;
component MAM_D is
generic (DigitalWidth : integer := 32); -- data width forDigital input
port (In_i : in std_logic_vector(DigitalWidth-1 downto 0);
En_i : in std_logic;
Through_i : in std_logic;
Clk : in std_logic;
Reset : in std_logic;
Min_o : out std_logic_vector(DigitalWidth-1 downto 0);
Max_o : out std_logic_vector(DigitalWidth-1 downto 0));
end component;
component Latch_A is
generic (AnalogWidth : integer := 10; -- width of analog signals
AverageWidth : integer := 32); -- width of averager output
port (Min_i : in std_logic_vector(AnalogWidth -1 downto 0);
Avg_i : in std_logic_vector(AverageWidth-1 downto 0);
Max_i : in std_logic_vector(AnalogWidth -1 downto 0);
Latch_i : in std_logic;
Clk : in std_logic;
Reset : in std_logic;
Min_o : out std_logic_vector(AnalogWidth -1 downto 0);
Avg_o : out std_logic_vector(AverageWidth-1 downto 0);
Max_o : out std_logic_vector(AnalogWidth -1 downto 0));
end component;
component Latch_D is
generic (DigitalWidth : integer := 32); -- data width for analog input/output
port(
Min_i : in std_logic_vector(DigitalWidth-1 downto 0);
Max_i : in std_logic_vector(DigitalWidth-1 downto 0);
Latch_i : in std_logic;
Clk : in std_logic;
Reset : in std_logic;
Min_o : out std_logic_vector(DigitalWidth-1 downto 0);
Max_o : out std_logic_vector(DigitalWidth-1 downto 0));
end component;
component MUX_AD is
generic (
AnalogWidth : integer := 10; -- width of analog signal (Min, Max)
AverageWidth : integer := 36; -- width of average signal
DigitalWidth : integer := 32; -- width of digital signals
RAM_Width : integer := 72); -- width of data bus to the RAM
port (
RAM_o : out std_logic_vector(RAM_Width -1 downto 0); -- outputs to the RAM
Min1_i : in std_logic_vector(AnalogWidth -1 downto 0); -- input of minimum of 1st channel
Avg1_i : in std_logic_vector(AverageWidth-1 downto 0); -- input of average of 1st channel
Max1_i : in std_logic_vector(AnalogWidth -1 downto 0); -- input of maximum of 1st channel
Min2_i : in std_logic_vector(AnalogWidth -1 downto 0); -- input of minimum of 2nd channel
Avg2_i : in std_logic_vector(AverageWidth-1 downto 0); -- input of average of 2nd channel
Max2_i : in std_logic_vector(AnalogWidth -1 downto 0); -- input of maximum of 2nd channel
Min3_i : in std_logic_vector(AnalogWidth -1 downto 0); -- input of minimum of 3rd channel
Avg3_i : in std_logic_vector(AverageWidth-1 downto 0); -- input of average of 3rd channel
Max3_i : in std_logic_vector(AnalogWidth -1 downto 0); -- input of maximum of 3rd channel
Min4_i : in std_logic_vector(AnalogWidth -1 downto 0); -- input of minimum of 4th channel
Avg4_i : in std_logic_vector(AverageWidth-1 downto 0); -- input of average of 4th channel
Max4_i : in std_logic_vector(AnalogWidth -1 downto 0); -- input of maximum of 4th channel
MinD_i : in std_logic_vector(DigitalWidth-1 downto 0); -- input of minimum of digital channel
MaxD_i : in std_logic_vector(DigitalWidth-1 downto 0); -- input of maximum of digital channel
MAAM_i : in MAAM_t); -- select data bit group
end component;
component MUX_RAM is
generic (
RAM_Width : integer := 72 -- width of data bus to RAM
);
port (
RAM_Dir_i : in std_logic; -- direction of data switch
AD_i : in std_logic_vector(RAM_Width-1 downto 0); -- data from ADC and digital inputs
PP_o : out std_logic_vector(RAM_Width-1 downto 0); -- data to micro processor
RAM_b : inout std_logic_vector(RAM_Width-1 downto 0)); -- data bus to RAM
end component;
component DEMUX_PP is
generic (
AnalogWidth : integer := 10; -- width of analog signal (Min, Max)
AverageWidth : integer := 36; -- width of average signal
DigitalWidth : integer := 32; -- width of digital signals
RAM_Width : integer := 72); -- width of data bus to the RAM
port (
RAM_i : in std_logic_vector(RAM_Width -1 downto 0); -- outputs to the RAM
Min1_o : out std_logic_vector(AnalogWidth -1 downto 0); -- output of minimum of 1st channel
Avg1_o : out std_logic_vector(AverageWidth-1 downto 0); -- output of average of 1st channel
Max1_o : out std_logic_vector(AnalogWidth -1 downto 0); -- output of maximum of 1st channel
Min2_o : out std_logic_vector(AnalogWidth -1 downto 0); -- output of minimum of 2nd channel
Avg2_o : out std_logic_vector(AverageWidth-1 downto 0); -- output of average of 2nd channel
Max2_o : out std_logic_vector(AnalogWidth -1 downto 0); -- output of maximum of 2nd channel
Min3_o : out std_logic_vector(AnalogWidth -1 downto 0); -- output of minimum of 3rd channel
Avg3_o : out std_logic_vector(AverageWidth-1 downto 0); -- output of average of 3rd channel
Max3_o : out std_logic_vector(AnalogWidth -1 downto 0); -- output of maximum of 3rd channel
Min4_o : out std_logic_vector(AnalogWidth -1 downto 0); -- output of minimum of 4th channel
Avg4_o : out std_logic_vector(AverageWidth-1 downto 0); -- output of average of 4th channel
Max4_o : out std_logic_vector(AnalogWidth -1 downto 0); -- output of maximum of 4th channel
MinD_o : out std_logic_vector(DigitalWidth-1 downto 0); -- output of minimum of digital channels
MaxD_o : out std_logic_vector(DigitalWidth-1 downto 0) -- output of maximum of digital channels
-- MAM_i : in std_logic); -- tell the Demux
); -- if the data from RAM has been MAM'ed or not
end component;
component MAM_A_P is
generic (AnalogWidth : integer := 10; -- data width for analog input/output
AverageWidth : integer := 36); -- data width for Avg-output
port (Min_i : in std_logic_vector(AnalogWidth -1 downto 0);
Avg_i : in std_logic_vector(AverageWidth-1 downto 0);
Max_i : in std_logic_vector(AnalogWidth -1 downto 0);
EnMin_i : in std_logic;
EnAvg_i : in std_logic;
EnMax_i : in std_logic;
Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
Clk : in std_logic;
Reset : in std_logic;
Min_o : out std_logic_vector(AnalogWidth -1 downto 0);
Avg_o : out std_logic_vector(AverageWidth-1 downto 0);
Max_o : out std_logic_vector(AnalogWidth -1 downto 0));
end component;
component MAM_D_P is
generic(
DigitalWidth : integer := 32);
port(
Min_i : in std_logic_vector(DigitalWidth-1 downto 0);
Max_i : in std_logic_vector(DigitalWidth-1 downto 0);
EnMax_i : in std_logic;
EnMin_i : in std_logic;
Through_i : in std_logic;
Clk : in std_logic;
Reset : in std_logic;
Min_o : out std_logic_vector(DigitalWidth-1 downto 0);
Max_o : out std_logic_vector(DigitalWidth-1 downto 0));
end component;
component PP_Clk is
port (
MAAM_i : in MAAM_t; -- select input
EnMin_o : out std_logic; -- selects the minima
EnAvg1_o : out std_logic; -- selects the first averages
EnAvg2_o : out std_logic; -- selects the second averages
EnMax_o : out std_logic); -- selects the maxima
end component;
component MUX_uC is
-- generic (
-- Width : Integer := 72); -- data path width
port (
PP_i : in std_logic_vector(71 downto 0); -- input (data path, from post processing)
uC_o : out std_logic_vector( 7 downto 0); -- output (to µC)
Select_i : in std_logic_vector( 3 downto 0)); -- select the section from the data path
end component;
signal Min_Ch1 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_Ch1 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_Ch1 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_Ch2 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_Ch2 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_Ch2 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_Ch3 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_Ch3 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_Ch3 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_Ch4 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_Ch4 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_Ch4 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_Dig : std_logic_vector(DigitalWidth-1 downto 0);
signal Max_Dig : std_logic_vector(DigitalWidth-1 downto 0);
signal Min_L_Ch1 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_L_Ch1 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_L_Ch1 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_L_Ch2 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_L_Ch2 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_L_Ch2 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_L_Ch3 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_L_Ch3 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_L_Ch3 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_L_Ch4 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_L_Ch4 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_L_Ch4 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_L_Dig : std_logic_vector(DigitalWidth-1 downto 0);
signal Max_L_Dig : std_logic_vector(DigitalWidth-1 downto 0);
signal RAM_AD : std_logic_vector(RAM_Width-1 downto 0); -- signal from MUX_AD to MUX_RAM
signal RAM_PP : std_logic_vector(RAM_Width-1 downto 0); -- signal from MUX_RAM to DEMUX_PP
signal Min_D_Ch1 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_D_Ch1 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_D_Ch1 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_D_Ch2 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_D_Ch2 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_D_Ch2 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_D_Ch3 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_D_Ch3 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_D_Ch3 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_D_Ch4 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_D_Ch4 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_D_Ch4 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_D_Dig : std_logic_vector(DigitalWidth-1 downto 0);
signal Max_D_Dig : std_logic_vector(DigitalWidth-1 downto 0);
signal RAM_uC : std_logic_vector(RAM_Width-1 downto 0); -- signal from MUX_AD to MUX_uC
signal Min_P_Ch1 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_P_Ch1 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_P_Ch1 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_P_Ch2 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_P_Ch2 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_P_Ch2 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_P_Ch3 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_P_Ch3 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_P_Ch3 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_P_Ch4 : std_logic_vector(AnalogWidth -1 downto 0);
signal Avg_P_Ch4 : std_logic_vector(AverageWidth-1 downto 0);
signal Max_P_Ch4 : std_logic_vector(AnalogWidth -1 downto 0);
signal Min_P_Dig : std_logic_vector(DigitalWidth-1 downto 0);
signal Max_P_Dig : std_logic_vector(DigitalWidth-1 downto 0);
signal EnMin : std_logic; -- for MAM_[AD]_P
signal EnAvg1 : std_logic; -- for MAM_A_P
signal EnAvg2 : std_logic; -- for MAM_A_P
signal EnMax : std_logic; -- for MAM_[AD]_P
begin -- struc
i_MAM_A_Ch1 : MAM_A
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth)
port map (
In_i => Ch1_i,
Min_o => Min_Ch1,
Avg_o => Avg_Ch1,
Max_o => Max_Ch1,
En_i => En_AD_i,
Through_i => Through_AD_i,
Clk => Clk,
Reset => Reset);
i_MAM_A_Ch2 : MAM_A
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth)
port map (
In_i => Ch2_i,
Min_o => Min_Ch2,
Avg_o => Avg_Ch2,
Max_o => Max_Ch2,
En_i => En_AD_i,
Through_i => Through_AD_i,
Clk => Clk,
Reset => Reset);
i_MAM_A_Ch3 : MAM_A
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth)
port map (
In_i => Ch3_i,
Min_o => Min_Ch3,
Avg_o => Avg_Ch3,
Max_o => Max_Ch3,
En_i => En_AD_i,
Through_i => Through_AD_i,
Clk => Clk,
Reset => Reset);
i_MAM_A_Ch4 : MAM_A
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth)
port map (
In_i => Ch4_i,
Min_o => Min_Ch4,
Avg_o => Avg_Ch4,
Max_o => Max_Ch4,
En_i => En_AD_i,
Through_i => Through_AD_i,
Clk => Clk,
Reset => Reset);
i_MAM_D_Dig : MAM_D
generic map (
DigitalWidth => DigitalWidth)
port map (
In_i => Dig_i,
Min_o => Min_Dig,
Max_o => Max_Dig,
En_i => En_AD_i,
Through_i => Through_AD_i,
Clk => Clk,
Reset => Reset);
i_Latch_A_Ch1 : Latch_A
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth)
port map (
Min_i => Min_Ch1,
Avg_i => Avg_Ch1,
Max_i => Max_Ch1,
Min_o => Min_L_Ch1,
Avg_o => Avg_L_Ch1,
Max_o => Max_L_Ch1,
Latch_i => Latch_AD_i,
Clk => Clk,
Reset => Reset);
i_Latch_A_Ch2 : Latch_A
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth)
port map (
Min_i => Min_Ch2,
Avg_i => Avg_Ch2,
Max_i => Max_Ch2,
Min_o => Min_L_Ch2,
Avg_o => Avg_L_Ch2,
Max_o => Max_L_Ch2,
Latch_i => Latch_AD_i,
Clk => Clk,
Reset => Reset);
i_Latch_A_Ch3 : Latch_A
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth)
port map (
Min_i => Min_Ch3,
Avg_i => Avg_Ch3,
Max_i => Max_Ch3,
Min_o => Min_L_Ch3,
Avg_o => Avg_L_Ch3,
Max_o => Max_L_Ch3,
Latch_i => Latch_AD_i,
Clk => Clk,
Reset => Reset);
i_Latch_A_Ch4 : Latch_A
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth)
port map (
Min_i => Min_Ch4,
Avg_i => Avg_Ch4,
Max_i => Max_Ch4,
Min_o => Min_L_Ch4,
Avg_o => Avg_L_Ch4,
Max_o => Max_L_Ch4,
Latch_i => Latch_AD_i,
Clk => Clk,
Reset => Reset);
i_Latch_D_Dig : Latch_D
generic map (
DigitalWidth => DigitalWidth)
port map (
Min_i => Min_Dig,
Max_i => Max_Dig,
Min_o => Min_L_Dig,
Max_o => Max_L_Dig,
Latch_i => Latch_AD_i,
Clk => Clk,
Reset => Reset);
i_MUX_AD : MUX_AD
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth,
DigitalWidth => DigitalWidth,
RAM_Width => RAM_Width)
port map (
Min1_i => Min_L_Ch1,
Avg1_i => Avg_L_Ch1,
Max1_i => Max_L_Ch1,
Min2_i => Min_L_Ch2,
Avg2_i => Avg_L_Ch2,
Max2_i => Max_L_Ch2,
Min3_i => Min_L_Ch3,
Avg3_i => Avg_L_Ch3,
Max3_i => Max_L_Ch3,
Min4_i => Min_L_Ch4,
Avg4_i => Avg_L_Ch4,
Max4_i => Max_L_Ch4,
MinD_i => Min_L_Dig,
MaxD_i => Max_L_Dig,
RAM_o => RAM_AD,
MAAM_i => MAAM_AD_i);
i_MUX_RAM : MUX_RAM
generic map (
RAM_Width => RAM_Width)
port map (
AD_i => RAM_AD,
RAM_b => RAM_b,
PP_o => RAM_PP,
RAM_Dir_i => RAM_Dir_i);
i_DEMUX_PP : DEMUX_PP
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth,
DigitalWidth => DigitalWidth,
RAM_Width => RAM_Width)
port map (
Min1_o => Min_D_Ch1,
Avg1_o => Avg_D_Ch1,
Max1_o => Max_D_Ch1,
Min2_o => Min_D_Ch2,
Avg2_o => Avg_D_Ch2,
Max2_o => Max_D_Ch2,
Min3_o => Min_D_Ch3,
Avg3_o => Avg_D_Ch3,
Max3_o => Max_D_Ch3,
Min4_o => Min_D_Ch4,
Avg4_o => Avg_D_Ch4,
Max4_o => Max_D_Ch4,
MinD_o => Min_D_Dig,
MaxD_o => Max_D_Dig,
RAM_i => RAM_PP);
i_MAM_A_P_Ch1 : MAM_A_P
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth)
port map (
Min_i => Min_D_Ch1,
Avg_i => Avg_D_Ch1,
Max_i => Max_D_Ch1,
Min_o => Min_P_Ch1,
Avg_o => Avg_P_Ch1,
Max_o => Max_P_Ch1,
EnMin_i => EnMin,
EnAvg_i => EnAvg1,
EnMax_i => EnMax,
Through_i => Through_PP_i,
Clk => Clk,
Reset => Reset);
i_MAM_A_P_Ch2 : MAM_A_P
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth)
port map (
Min_i => Min_D_Ch2,
Avg_i => Avg_D_Ch2,
Max_i => Max_D_Ch2,
Min_o => Min_P_Ch2,
Avg_o => Avg_P_Ch2,
Max_o => Max_P_Ch2,
EnMin_i => EnMin,
EnAvg_i => EnAvg1,
EnMax_i => EnMax,
Through_i => Through_PP_i,
Clk => Clk,
Reset => Reset);
i_MAM_A_P_Ch3 : MAM_A_P
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth)
port map (
Min_i => Min_D_Ch3,
Avg_i => Avg_D_Ch3,
Max_i => Max_D_Ch3,
Min_o => Min_P_Ch3,
Avg_o => Avg_P_Ch3,
Max_o => Max_P_Ch3,
EnMin_i => EnMin,
EnAvg_i => EnAvg2,
EnMax_i => EnMax,
Through_i => Through_PP_i,
Clk => Clk,
Reset => Reset);
i_MAM_A_P_Ch4 : MAM_A_P
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth)
port map (
Min_i => Min_D_Ch4,
Avg_i => Avg_D_Ch4,
Max_i => Max_D_Ch4,
Min_o => Min_P_Ch4,
Avg_o => Avg_P_Ch4,
Max_o => Max_P_Ch4,
EnMin_i => EnMin,
EnAvg_i => EnAvg2,
EnMax_i => EnMax,
Through_i => Through_PP_i,
Clk => Clk,
Reset => Reset);
i_MAM_D_P_Dig : MAM_D_P
generic map (
DigitalWidth => DigitalWidth)
port map (
Min_i => Min_D_Dig,
Max_i => Max_D_Dig,
Min_o => Min_P_Dig,
Max_o => Max_P_Dig,
EnMin_i => EnMin,
EnMax_i => EnMax,
Through_i => Through_PP_i,
Clk => Clk,
Reset => Reset);
i_PP_Clk : PP_Clk
port map (
MAAM_i => MAAM_PP_i,
EnMin_o => EnMin,
EnAvg1_o => EnAvg1,
EnAvg2_o => EnAvg2,
EnMax_o => EnMax);
i_MUX_AD_PP : MUX_AD
generic map (
AnalogWidth => AnalogWidth,
AverageWidth => AverageWidth,
DigitalWidth => DigitalWidth,
RAM_Width => RAM_Width)
port map (
Min1_i => Min_P_Ch1,
Avg1_i => Avg_P_Ch1,
Max1_i => Max_P_Ch1,
Min2_i => Min_P_Ch2,
Avg2_i => Avg_P_Ch2,
Max2_i => Max_P_Ch2,
Min3_i => Min_P_Ch3,
Avg3_i => Avg_P_Ch3,
Max3_i => Max_P_Ch3,
Min4_i => Min_P_Ch4,
Avg4_i => Avg_P_Ch4,
Max4_i => Max_P_Ch4,
MinD_i => Min_P_Dig,
MaxD_i => Max_P_Dig,
RAM_o => RAM_uC,
MAAM_i => MAAM_PP_i);
i_MUX_uC : MUX_uC
port map (
PP_i => RAM_uC,
uC_o => uC_o,
Select_i => uC_Select_i);
end struc;
Index: Avg_A_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Avg_A_.vhd,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** Avg_A_.vhd 1 Apr 2003 08:48:41 -0000 1.6
--- Avg_A_.vhd 8 Apr 2003 13:25:11 -0000 1.7
***************
*** 29,47 ****
-------------------------------------------------------------------------------
! library IEEE;
use IEEE.std_logic_1164.all;
!
-----------------------------ENTITY DECLARATION--------------------------------
entity Avg_A is
!
! generic (WidthIn : integer := 10; -- data width for analog input
! WidthOut : integer := 36); -- data width for averager output
! port (In_i : in std_logic_vector(WidthIn-1 downto 0);
! En : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic;
! Through : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Out_o : out std_logic_vector(WidthOut-1 downto 0));
!
end Avg_A;
--- 29,48 ----
-------------------------------------------------------------------------------
! library IEEE;
use IEEE.std_logic_1164.all;
!
-----------------------------ENTITY DECLARATION--------------------------------
entity Avg_A is
!
! generic (WidthIn : Integer := 10; -- data width for analog input
! WidthOut : Integer := 36); -- data width for averager output
!
! port (In_i : in std_logic_vector(WidthIn-1 downto 0);
! En_i : in std_logic;
! Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector(WidthOut-1 downto 0));
!
end Avg_A;
Index: Avg_A_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Avg_A_rtl.vhd,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** Avg_A_rtl.vhd 1 Apr 2003 11:53:35 -0000 1.8
--- Avg_A_rtl.vhd 8 Apr 2003 13:25:15 -0000 1.9
***************
*** 49,58 ****
Avg_var := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
! if En = '1' then
-- preferably that should be synthesized as a multiplexer
-- XST doesn't :-( !!!FIXME!!!
! if Through = '1' then
Avg_var(WidthIn -1 downto 0) := In_i;
! Avg_var(WidthOut-1 downto WidthIn) := (others => '0');
else
Avg_var := Avg_var + sxt(In_i, WidthOut);
--- 49,60 ----
Avg_var := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
! if En_i = '1' then
-- preferably that should be synthesized as a multiplexer
-- XST doesn't :-( !!!FIXME!!!
! if Through_i = '1' then
Avg_var(WidthIn -1 downto 0) := In_i;
! if WidthOut > WidthIn then
! Avg_var(WidthOut-1 downto WidthIn) := (others => '0');
! end if;
else
Avg_var := Avg_var + sxt(In_i, WidthOut);
Index: Latch_D_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Latch_D_.vhd,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** Latch_D_.vhd 26 Feb 2003 12:11:54 -0000 1.5
--- Latch_D_.vhd 8 Apr 2003 13:25:16 -0000 1.6
***************
*** 36,51 ****
generic (DigitalWidth : integer := 32); -- data width for analog input/output
-
port(
Min_i : in std_logic_vector(DigitalWidth-1 downto 0);
-
Max_i : in std_logic_vector(DigitalWidth-1 downto 0);
Latch_i : in std_logic;
Clk : in std_logic;
-
Reset : in std_logic;
Min_o : out std_logic_vector(DigitalWidth-1 downto 0);
-
Max_o : out std_logic_vector(DigitalWidth-1 downto 0));
--- 36,47 ----
Index: MAM_A_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MAM_A_.vhd,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** MAM_A_.vhd 1 Apr 2003 08:48:41 -0000 1.4
--- MAM_A_.vhd 8 Apr 2003 13:25:17 -0000 1.5
***************
*** 39,51 ****
AverageWidth : integer := 36); -- data width for Avg-output
! port (In_i : in std_logic_vector(AnalogWidth-1 downto 0);
! En : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic;
! Through : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
!
! Min_o : out std_logic_vector(AnalogWidth -1 downto 0);
! Avg_o : out std_logic_vector(AverageWidth-1 downto 0);
! Max_o : out std_logic_vector(AnalogWidth -1 downto 0));
end MAM_A;
--- 39,50 ----
AverageWidth : integer := 36); -- data width for Avg-output
! port (In_i : in std_logic_vector(AnalogWidth-1 downto 0);
! En_i : in std_logic;
! Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Min_o : out std_logic_vector(AnalogWidth -1 downto 0);
! Avg_o : out std_logic_vector(AverageWidth-1 downto 0);
! Max_o : out std_logic_vector(AnalogWidth -1 downto 0));
end MAM_A;
Index: MAM_A_P_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MAM_A_P_.vhd,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** MAM_A_P_.vhd 1 Apr 2003 08:48:41 -0000 1.5
--- MAM_A_P_.vhd 8 Apr 2003 13:25:17 -0000 1.6
***************
*** 39,55 ****
AverageWidth : integer := 36); -- data width for Avg-output
! port (Min_i : in std_logic_vector(AnalogWidth -1 downto 0);
! Avg_i : in std_logic_vector(AverageWidth-1 downto 0);
! Max_i : in std_logic_vector(AnalogWidth -1 downto 0);
! EnMin : in std_logic;
! EnAvg : in std_logic;
! EnMax : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic;
! Through : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Min_o : out std_logic_vector(AnalogWidth -1 downto 0);
! Avg_o : out std_logic_vector(AverageWidth-1 downto 0);
! Max_o : out std_logic_vector(AnalogWidth -1 downto 0));
end MAM_A_P;
--- 39,55 ----
AverageWidth : integer := 36); -- data width for Avg-output
! port (Min_i : in std_logic_vector(AnalogWidth -1 downto 0);
! Avg_i : in std_logic_vector(AverageWidth-1 downto 0);
! Max_i : in std_logic_vector(AnalogWidth -1 downto 0);
! EnMin_i : in std_logic;
! EnAvg_i : in std_logic;
! EnMax_i : in std_logic;
! Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Min_o : out std_logic_vector(AnalogWidth -1 downto 0);
! Avg_o : out std_logic_vector(AverageWidth-1 downto 0);
! Max_o : out std_logic_vector(AnalogWidth -1 downto 0));
end MAM_A_P;
Index: MAM_A_P_struc.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MAM_A_P_struc.vhd,v
retrieving revision 1.9
retrieving revision 1.10
diff -C2 -d -r1.9 -r1.10
*** MAM_A_P_struc.vhd 1 Apr 2003 11:53:35 -0000 1.9
--- MAM_A_P_struc.vhd 8 Apr 2003 13:25:18 -0000 1.10
***************
*** 37,46 ****
Width : integer); -- data width of analog signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! Out_o : out std_logic_vector((Width-1) downto 0);
! En : in std_logic;
! Clk : in std_logic;
! Through : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Reset : in std_logic);
end component;
--- 37,46 ----
Width : integer); -- data width of analog signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! En_i : in std_logic;
! Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector((Width-1) downto 0));
end component;
***************
*** 50,59 ****
WidthOut : integer); -- data width of averager output
port (
! In_i : in std_logic_vector((WidthIn -1) downto 0);
! Out_o : out std_logic_vector((WidthOut-1) downto 0);
! En : in std_logic;
! Clk : in std_logic;
! Through : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Reset : in std_logic);
end component;
--- 50,59 ----
WidthOut : integer); -- data width of averager output
port (
! In_i : in std_logic_vector((WidthIn -1) downto 0);
! En_i : in std_logic;
! Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector((WidthOut-1) downto 0));
end component;
***************
*** 62,71 ****
Width : integer); -- data width of analog signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! Out_o : out std_logic_vector((Width-1) downto 0);
! En : in std_logic;
! Clk : in std_logic;
! Through : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Reset : in std_logic);
end component;
--- 62,71 ----
Width : integer); -- data width of analog signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! En_i : in std_logic;
! Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector((Width-1) downto 0));
end component;
***************
*** 76,85 ****
Width => AnalogWidth)
port map (
! In_i => Min_i,
! En => EnMin,
! Clk => Clk,
! Reset => Reset,
! Through => Through,
! Out_o => Min_o);
i_Avg_A : Avg_A
generic map(
--- 76,85 ----
Width => AnalogWidth)
port map (
! In_i => Min_i,
! En_i => EnMin_i,
! Through_i => Through_i,
! Clk => Clk,
! Reset => Reset,
! Out_o => Min_o);
i_Avg_A : Avg_A
generic map(
***************
*** 87,106 ****
WidthOut => AverageWidth)
port map (
! In_i => Avg_i,
! En => EnAvg,
! Clk => Clk,
! Reset => Reset,
! Through => Through,
! Out_o => Avg_o);
i_Max_A : Max_A
generic map (
Width => AnalogWidth)
port map (
! In_i => Max_i,
! En => EnMax,
! Clk => Clk,
! Reset => Reset,
! Through => Through,
! Out_o => Max_o);
end struc;
--- 87,106 ----
WidthOut => AverageWidth)
port map (
! In_i => Avg_i,
! En_i => EnAvg_i,
! Through_i => Through_i,
! Clk => Clk,
! Reset => Reset,
! Out_o => Avg_o);
i_Max_A : Max_A
generic map (
Width => AnalogWidth)
port map (
! In_i => Max_i,
! En_i => EnMax_i,
! Through_i => Through_i,
! Clk => Clk,
! Reset => Reset,
! Out_o => Max_o);
end struc;
Index: MAM_A_struc.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MAM_A_struc.vhd,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** MAM_A_struc.vhd 1 Apr 2003 08:48:41 -0000 1.7
--- MAM_A_struc.vhd 8 Apr 2003 13:25:18 -0000 1.8
***************
*** 32,68 ****
component Min_A
generic (
! Width : integer); -- data width of analog signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! Out_o : out std_logic_vector((Width-1) downto 0);
! Through : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! En : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic);
end component;
component Avg_A
generic (
! WidthIn : integer; -- data width of analog signal
! WidthOut: integer); -- data width of averager output
port (
! In_i : in std_logic_vector((WidthIn -1) downto 0);
! Out_o : out std_logic_vector((WidthOut-1) downto 0);
! Through : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! En : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic);
end component;
component Max_A
generic (
! Width : integer); -- data width of analog signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! Out_o : out std_logic_vector((Width-1) downto 0);
! Through : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! En : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic);
end component;
--- 32,68 ----
component Min_A
generic (
! Width : integer); -- data width of analog signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! En_i : in std_logic;
! Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector((Width-1) downto 0));
end component;
component Avg_A
generic (
! WidthIn : integer; -- data width of analog signal
! WidthOut : integer); -- data width of averager output
port (
! In_i : in std_logic_vector((WidthIn -1) downto 0);
! En_i : in std_logic;
! Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector((WidthOut-1) downto 0));
end component;
component Max_A
generic (
! Width : integer); -- data width of analog signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! En_i : in std_logic;
! Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector((Width-1) downto 0));
end component;
***************
*** 74,83 ****
Width => AnalogWidth)
port map (
! In_i => In_i,
! En => En,
! Clk => Clk,
! Reset => Reset,
! Through => Through,
! Out_o => Min_o);
i_Avg_A : Avg_A
generic map(
--- 74,83 ----
Width => AnalogWidth)
port map (
! In_i => In_i,
! En_i => En_i,
! Through_i => Through_i,
! Clk => Clk,
! Reset => Reset,
! Out_o => Min_o);
i_Avg_A : Avg_A
generic map(
***************
*** 85,104 ****
WidthOut => AverageWidth)
port map (
! In_i => In_i,
! En => En,
! Clk => Clk,
! Reset => Reset,
! Through => Through,
! Out_o => Avg_o);
i_Max_A : Max_A
generic map (
Width => AnalogWidth)
port map (
! In_i => In_i,
! En => En,
! Clk => Clk,
! Reset => Reset,
! Through => Through,
! Out_o => Max_o);
end struc;
--- 85,104 ----
WidthOut => AverageWidth)
port map (
! In_i => In_i,
! En_i => En_i,
! Through_i => Through_i,
! Clk => Clk,
! Reset => Reset,
! Out_o => Avg_o);
i_Max_A : Max_A
generic map (
Width => AnalogWidth)
port map (
! In_i => In_i,
! En_i => En_i,
! Through_i => Through_i,
! Clk => Clk,
! Reset => Reset,
! Out_o => Max_o);
end struc;
Index: MAM_D_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MAM_D_.vhd,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** MAM_D_.vhd 1 Apr 2003 11:53:35 -0000 1.5
--- MAM_D_.vhd 8 Apr 2003 13:25:19 -0000 1.6
***************
*** 38,49 ****
generic (DigitalWidth : Integer := 32); -- data width forDigital input
! port (In_i : in std_logic_vector(DigitalWidth-1 downto 0);
! En : in std_logic;
! Through : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic;
!
! Min_o : out std_logic_vector(DigitalWidth-1 downto 0);
! Max_o : out std_logic_vector(DigitalWidth-1 downto 0));
end MAM_D;
--- 38,49 ----
generic (DigitalWidth : Integer := 32); -- data width forDigital input
! port (In_i : in std_logic_vector(DigitalWidth-1 downto 0);
! En_i : in std_logic;
! Through_i : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic;
!
! Min_o : out std_logic_vector(DigitalWidth-1 downto 0);
! Max_o : out std_logic_vector(DigitalWidth-1 downto 0));
end MAM_D;
Index: MAM_D_P_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MAM_D_P_.vhd,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** MAM_D_P_.vhd 1 Apr 2003 11:53:35 -0000 1.5
--- MAM_D_P_.vhd 8 Apr 2003 13:25:20 -0000 1.6
***************
*** 40,55 ****
port(
! Min_i : in std_logic_vector(DigitalWidth-1 downto 0);
! Max_i : in std_logic_vector(DigitalWidth-1 downto 0);
!
! EnMax : in std_logic;
! EnMin : in std_logic;
! Through : in std_logic;
!
! Clk : in std_logic;
! Reset : in std_logic;
!
! Min_o : out std_logic_vector(DigitalWidth-1 downto 0);
! Max_o : out std_logic_vector(DigitalWidth-1 downto 0));
end MAM_D_P;
--- 40,55 ----
port(
! Min_i : in std_logic_vector(DigitalWidth-1 downto 0);
! Max_i : in std_logic_vector(DigitalWidth-1 downto 0);
!
! EnMax_i : in std_logic;
! EnMin_i : in std_logic;
! Through_i : in std_logic;
!
! Clk : in std_logic;
! Reset : in std_logic;
!
! Min_o : out std_logic_vector(DigitalWidth-1 downto 0);
! Max_o : out std_logic_vector(DigitalWidth-1 downto 0));
end MAM_D_P;
Index: MAM_D_P_struc.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MAM_D_P_struc.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** MAM_D_P_struc.vhd 1 Apr 2003 11:53:35 -0000 1.3
--- MAM_D_P_struc.vhd 8 Apr 2003 13:25:20 -0000 1.4
***************
*** 34,43 ****
Width : integer); -- data width of digital signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! Out_o : out std_logic_vector((Width-1) downto 0);
! En : in std_logic;
! Through : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic);
end component;
--- 34,43 ----
Width : integer); -- data width of digital signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! En_i : in std_logic;
! Through_i : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector((Width-1) downto 0));
end component;
***************
*** 46,55 ****
Width : integer); -- data width of digital signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! Out_o : out std_logic_vector((Width-1) downto 0);
! En : in std_logic;
! Through : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic);
end component;
--- 46,55 ----
Width : integer); -- data width of digital signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! En_i : in std_logic;
! Through_i : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector((Width-1) downto 0));
end component;
***************
*** 61,70 ****
Width => DigitalWidth)
port map (
! In_i => Min_i,
! En => EnMin,
! Through => Through,
! Clk => Clk,
! Reset => Reset,
! Out_o => Min_o);
i_Max_D : Max_D
--- 61,70 ----
Width => DigitalWidth)
port map (
! In_i => Min_i,
! En_i => EnMin_i,
! Through_i => Through_i,
! Clk => Clk,
! Reset => Reset,
! Out_o => Min_o);
i_Max_D : Max_D
***************
*** 72,81 ****
Width => DigitalWidth)
port map (
! In_i => Max_i,
! En => EnMax,
! Through => Through,
! Clk => Clk,
! Reset => Reset,
! Out_o => Max_o);
end struc;
--- 72,81 ----
Width => DigitalWidth)
port map (
! In_i => Max_i,
! En_i => EnMax_i,
! Through_i => Through_i,
! Clk => Clk,
! Reset => Reset,
! Out_o => Max_o);
end struc;
Index: MAM_D_struc.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MAM_D_struc.vhd,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** MAM_D_struc.vhd 1 Apr 2003 11:53:35 -0000 1.5
--- MAM_D_struc.vhd 8 Apr 2003 13:25:20 -0000 1.6
***************
*** 34,43 ****
Width : integer); -- data width of digital signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! Out_o : out std_logic_vector((Width-1) downto 0);
! En : in std_logic;
! Through : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic);
end component;
--- 34,43 ----
Width : integer); -- data width of digital signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! En_i : in std_logic;
! Through_i : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector((Width-1) downto 0));
end component;
***************
*** 46,55 ****
Width : integer); -- data width of digital signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! Out_o : out std_logic_vector((Width-1) downto 0);
! En : in std_logic;
! Through : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic);
end component;
--- 46,55 ----
Width : integer); -- data width of digital signal
port (
! In_i : in std_logic_vector((Width-1) downto 0);
! En_i : in std_logic;
! Through_i : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector((Width-1) downto 0));
end component;
***************
*** 61,81 ****
Width => DigitalWidth)
port map (
! In_i => In_i,
! En => En,
! Through => Through,
! Clk => Clk,
! Reset => Reset,
! Out_o => Min_o);
!
i_Max_D : Max_D
generic map (
Width => DigitalWidth)
port map (
! In_i => In_i,
! En => En,
! Through => Through,
! Clk => Clk,
! Reset => Reset,
! Out_o => Max_o);
end struc;
--- 61,81 ----
Width => DigitalWidth)
port map (
! In_i => In_i,
! En_i => En_i,
! Through_i => Through_i,
! Clk => Clk,
! Reset => Reset,
! Out_o => Min_o);
!
i_Max_D : Max_D
generic map (
Width => DigitalWidth)
port map (
! In_i => In_i,
! En_i => En_i,
! Through_i => Through_i,
! Clk => Clk,
! Reset => Reset,
! Out_o => Max_o);
end struc;
Index: Max_A_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Max_A_.vhd,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** Max_A_.vhd 1 Apr 2003 08:48:41 -0000 1.4
--- Max_A_.vhd 8 Apr 2003 13:25:20 -0000 1.5
***************
*** 38,48 ****
generic (Width : integer := 10); -- data width for analog input/output
! port (In_i : in std_logic_vector(Width-1 downto 0);
! En : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic;
! Through : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
!
! Out_o : out std_logic_vector(Width-1 downto 0));
end Max_A;
--- 38,47 ----
generic (Width : integer := 10); -- data width for analog input/output
! port (In_i : in std_logic_vector(Width-1 downto 0);
! En_i : in std_logic;
! Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector(Width-1 downto 0));
end Max_A;
Index: Max_A_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Max_A_rtl.vhd,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** Max_A_rtl.vhd 1 Apr 2003 09:13:43 -0000 1.5
--- Max_A_rtl.vhd 8 Apr 2003 13:25:20 -0000 1.6
***************
*** 47,52 ****
MaxVar := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
! if En = '1' then
! if IEEE.std_logic_signed.">"(In_i,MaxVar) or (Through = '1') then
MaxVar := In_i;
end if;
--- 47,52 ----
MaxVar := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
! if En_i = '1' then
! if IEEE.std_logic_signed.">"(In_i,MaxVar) or (Through_i = '1') then
MaxVar := In_i;
end if;
Index: Max_D_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Max_D_.vhd,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** Max_D_.vhd 1 Apr 2003 09:13:44 -0000 1.5
--- Max_D_.vhd 8 Apr 2003 13:25:21 -0000 1.6
***************
*** 39,48 ****
generic (Width : integer := 32); -- data width fo rdigital input/output
! port (In_i : in std_logic_vector(Width-1 downto 0);
! En : in std_logic;
! Through : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector(Width-1 downto 0));
end Max_D;
--- 39,48 ----
generic (Width : integer := 32); -- data width fo rdigital input/output
! port (In_i : in std_logic_vector(Width-1 downto 0);
! En_i : in std_logic;
! Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector(Width-1 downto 0));
end Max_D;
Index: Max_D_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Max_D_rtl.vhd,v
retrieving revision 1.9
retrieving revision 1.10
diff -C2 -d -r1.9 -r1.10
*** Max_D_rtl.vhd 1 Apr 2003 11:53:35 -0000 1.9
--- Max_D_rtl.vhd 8 Apr 2003 13:25:22 -0000 1.10
***************
*** 49,55 ****
Max_var := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
! if En = '1' then
for i in Width-1 downto 0 loop
! Feedback(i) := Max_var(i) and not Through;
end loop;
Max_var := In_i or Feedback;
--- 49,55 ----
Max_var := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
! if En_i = '1' then
for i in Width-1 downto 0 loop
! Feedback(i) := Max_var(i) and not Through_i;
end loop;
Max_var := In_i or Feedback;
Index: Min_A_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Min_A_.vhd,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** Min_A_.vhd 1 Apr 2003 07:57:27 -0000 1.7
--- Min_A_.vhd 8 Apr 2003 13:25:23 -0000 1.8
***************
*** 39,48 ****
generic (Width : integer := 10); -- data width for analog input/output
! port (In_i : in std_logic_vector(Width-1 downto 0);
! En : in std_logic;
! Clk : in std_logic;
! Reset : in std_logic;
! Through : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Out_o : out std_logic_vector(Width-1 downto 0));
end Min_A;
--- 39,48 ----
generic (Width : integer := 10); -- data width for analog input/output
! port (In_i : in std_logic_vector(Width-1 downto 0);
! En_i : in std_logic;
! Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector(Width-1 downto 0));
end Min_A;
Index: Min_A_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Min_A_rtl.vhd,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** Min_A_rtl.vhd 1 Apr 2003 07:57:27 -0000 1.6
--- Min_A_rtl.vhd 8 Apr 2003 13:25:23 -0000 1.7
***************
*** 47,52 ****
MinVar := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
! if En = '1' then
! if IEEE.std_logic_signed."<"(In_i,MinVar) or (Through = '1') then
MinVar := In_i;
end if;
--- 47,52 ----
MinVar := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
! if En_i = '1' then
! if IEEE.std_logic_signed."<"(In_i,MinVar) or (Through_i = '1') then
MinVar := In_i;
end if;
Index: Min_D_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Min_D_.vhd,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** Min_D_.vhd 1 Apr 2003 09:13:44 -0000 1.5
--- Min_D_.vhd 8 Apr 2003 13:25:23 -0000 1.6
***************
*** 39,48 ****
generic (Width : integer := 32); -- data width for analog input/output
! port (In_i : in std_logic_vector(Width-1 downto 0);
! En : in std_logic;
! Through : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector(Width-1 downto 0));
end Min_D;
--- 39,48 ----
generic (Width : integer := 32); -- data width for analog input/output
! port (In_i : in std_logic_vector(Width-1 downto 0);
! En_i : in std_logic;
! Through_i : in std_logic; -- Out_o <= In_o at rising_edge(Clk)
! Clk : in std_logic;
! Reset : in std_logic;
! Out_o : out std_logic_vector(Width-1 downto 0));
end Min_D;
Index: Min_D_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Min_D_rtl.vhd,v
retrieving revision 1.9
retrieving revision 1.10
diff -C2 -d -r1.9 -r1.10
*** Min_D_rtl.vhd 1 Apr 2003 11:53:35 -0000 1.9
--- Min_D_rtl.vhd 8 Apr 2003 13:25:23 -0000 1.10
***************
*** 49,55 ****
Min_var := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
! if En = '1' then
for i in Width-1 downto 0 loop
! Feedback(i) := Min_var(i) or Through;
end loop;
Min_var := In_i and Feedback;
--- 49,55 ----
Min_var := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
! if En_i = '1' then
for i in Width-1 downto 0 loop
! Feedback(i) := Min_var(i) or Through_i;
end loop;
Min_var := In_i and Feedback;
Index: Trigger_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Trigger_.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** Trigger_.vhd 25 Mar 2003 09:31:32 -0000 1.3
--- Trigger_.vhd 8 Apr 2003 13:25:24 -0000 1.4
***************
*** 40,56 ****
AnalogWidth : integer := 10; -- the Width of the analog signal
DigitalWidth : integer := 32; -- the width of digital signals
! ADDRWidth : Integer := 6; -- address width
DataWidth : Integer := 8); -- Bidirectional Data
port (
! CH1_i : in std_logic_vector(AnalogWidth-1 downto 0);
! CH2_i : in std_logic_vector(AnalogWidth-1 downto 0);
! CH3_i : in std_logic_vector(AnalogWidth-1 downto 0);
! CH4_i : in std_logic_vector(AnalogWidth-1 downto 0);
! Digital_i : in std_logic_vector(DigitalWidth-1 downto 0);
! Addr_i : in std_logic_vector(DigitalWidth-1 downto 0);
! Data_b : inout std_logic_vector(ADDRWidth-1 downto 0);
! WR_i : in std_logic_bit;
! Trigger_o : out std_logic_bit);
end Trigger;
--- 40,59 ----
AnalogWidth : integer := 10; -- the Width of the analog signal
DigitalWidth : integer := 32; -- the width of digital signals
! AddrWidth : Integer := 6; -- address width
DataWidth : Integer := 8); -- Bidirectional Data
port...
[truncated message content] |
|
From: Johann G. <han...@us...> - 2003-04-08 13:25:46
|
Update of /cvsroot/dso/FPGA/Synplify In directory sc8-pr-cvs1:/tmp/cvs-serv1806/Synplify Modified Files: project.prd project.prj Log Message: Renamed signals "Through" to "Through_i" and "En" to "En_i". Added entity and architecture of Datapath. Index: project.prd =================================================================== RCS file: /cvsroot/dso/FPGA/Synplify/project.prd,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** project.prd 5 Apr 2003 10:00:57 -0000 1.1 --- project.prd 8 Apr 2003 13:25:08 -0000 1.2 *************** *** 2,6 **** #-- Version 7.0.3 #-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prd ! #-- Written on Sat Apr 5 11:53:16 2003 # --- 2,6 ---- #-- Version 7.0.3 #-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prd ! #-- Written on Sat Apr 5 18:08:02 2003 # Index: project.prj =================================================================== RCS file: /cvsroot/dso/FPGA/Synplify/project.prj,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** project.prj 5 Apr 2003 10:00:57 -0000 1.1 --- project.prj 8 Apr 2003 13:25:09 -0000 1.2 *************** *** 2,30 **** #-- Version 7.0.3 #-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prj ! #-- Written on Sat Apr 5 11:53:16 2003 #add_file options add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/types_p.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Reg_N_Load_8_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Reg_N_Load_8_rtl.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Avg_A_.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Avg_A_rtl.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/DownCounter_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/DownCounter_rtl.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/CountDown_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/CountDown_struc.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Join_MinMax_.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Join_MinMax_struc.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Join_Avg_.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Join_Avg_struc.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_AD_.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_AD_rtl.vhd" #reporting options ! #implementation: "Reg_N_Load_8" ! impl -add Reg_N_Load_8 #device options --- 2,64 ---- #-- Version 7.0.3 #-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prj ! #-- Written on Sat Apr 5 18:08:02 2003 #add_file options add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/types_p.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Min_A_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Min_A_rtl.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Avg_A_.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Avg_A_rtl.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Max_A_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Max_A_rtl.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MAM_A_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MAM_A_struc.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MAM_A_P_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MAM_A_P_struc.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Latch_A_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Latch_A_rtl.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Min_D_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Min_D_rtl.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Max_D_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Max_D_rtl.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MAM_D_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MAM_D_struc.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MAM_D_P_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MAM_D_P_struc.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Latch_D_.vhd" ! add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Latch_D_rtl.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Join_MinMax_.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Join_MinMax_struc.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Join_Avg_.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Join_Avg_struc.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_4_N_.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_4_N_rtl.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_AD_.vhd" add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_AD_rtl.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/DEMUX_PP_.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/DEMUX_PP_rtl.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_RAM_.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_RAM_rtl.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_uC_.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_uC_rtl.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/PP_Clk_.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/PP_Clk_rtl.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/DownCounter_.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/DownCounter_rtl.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Reg_N_Load_8_.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Reg_N_Load_8_rtl.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/CountDown_.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/CountDown_struc.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/UpCounter_.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/UpCounter_rtl.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Datapath_.vhd" + add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Datapath_struc.vhd" #reporting options ! #implementation: "CountDown" ! impl -add CountDown #device options *************** *** 38,42 **** set_option -symbolic_fsm_compiler 1 set_option -resource_sharing 1 ! set_option -top_module "Reg_N_Load_8" #map options --- 72,76 ---- set_option -symbolic_fsm_compiler 1 set_option -resource_sharing 1 ! set_option -top_module "CountDown" #map options *************** *** 55,63 **** #set result format/file last ! project -result_file "Reg_N_Load_8/rev_1.edf" ! #implementation: "CountDown" ! impl -add CountDown #device options --- 89,130 ---- #set result format/file last ! project -result_file "CountDown/rev_1.edf" ! #implementation: "MUX_AD" ! impl -add MUX_AD ! ! #device options ! set_option -technology VIRTEX2 ! set_option -part XC2V250 ! set_option -package CS144 ! set_option -speed_grade -5 ! ! #compilation/mapping options ! set_option -default_enum_encoding onehot ! set_option -symbolic_fsm_compiler 1 ! set_option -resource_sharing 1 ! set_option -top_module "MUX_AD" ! ! #map options ! set_option -frequency 0.000 ! set_option -fanout_limit 100 ! set_option -disable_io_insertion 0 ! set_option -pipe 0 ! set_option -retiming 0 ! ! #simulation options ! set_option -write_verilog 0 ! set_option -write_vhdl 0 ! ! #automatic place and route (vendor) options ! set_option -write_apr_constraint 1 ! ! #set result format/file last ! project -result_file "MUX_AD/rev_1.edf" ! ! ! #implementation: "MAM_A" ! impl -add MAM_A #device options *************** *** 71,75 **** set_option -symbolic_fsm_compiler 1 set_option -resource_sharing 1 ! set_option -top_module "CountDown" #map options --- 138,142 ---- set_option -symbolic_fsm_compiler 1 set_option -resource_sharing 1 ! set_option -top_module "MAM_A" #map options *************** *** 88,96 **** #set result format/file last ! project -result_file "CountDown/MUX_AD_rtl.edf" ! #implementation: "MUX_AD" ! impl -add MUX_AD #device options --- 155,361 ---- #set result format/file last ! project -result_file "MAM_A/rev_1.edf" ! #implementation: "MAM_A_P" ! impl -add MAM_A_P ! ! #device options ! set_option -technology VIRTEX2 ! set_option -part XC2V250 ! set_option -package CS144 ! set_option -speed_grade -5 ! ! #compilation/mapping options ! set_option -default_enum_encoding default ! set_option -symbolic_fsm_compiler 1 ! set_option -resource_sharing 1 ! set_option -top_module "MAM_A_P" ! ! #map options ! set_option -frequency 0.000 ! set_option -fanout_limit 100 ! set_option -disable_io_insertion 0 ! set_option -pipe 0 ! set_option -retiming 0 ! ! #simulation options ! set_option -write_verilog 0 ! set_option -write_vhdl 0 ! ! #automatic place and route (vendor) options ! set_option -write_apr_constraint 1 ! ! #set result format/file last ! project -result_file "MAM_A_P/rev_1.edf" ! ! ! #implementation: "Latch_A" ! impl -add Latch_A ! ! #device options ! set_option -technology VIRTEX2 ! set_option -part XC2V250 ! set_option -package CS144 ! set_option -speed_grade -5 ! ! #compilation/mapping options ! set_option -default_enum_encoding default ! set_option -symbolic_fsm_compiler 1 ! set_option -resource_sharing 1 ! set_option -top_module "Latch_A" ! ! #map options ! set_option -frequency 0.000 ! set_option -fanout_limit 100 ! set_option -disable_io_insertion 0 ! set_option -pipe 0 ! set_option -retiming 0 ! ! #simulation options ! set_option -write_verilog 0 ! set_option -write_vhdl 0 ! ! #automatic place and route (vendor) options ! set_option -write_apr_constraint 1 ! ! #set result format/file last ! project -result_file "Latch_A/rev_1.edf" ! ! ! #implementation: "MAM_D" ! impl -add MAM_D ! ! #device options ! set_option -technology VIRTEX2 ! set_option -part XC2V250 ! set_option -package CS144 ! set_option -speed_grade -5 ! ! #compilation/mapping options ! set_option -default_enum_encoding default ! set_option -symbolic_fsm_compiler 1 ! set_option -resource_sharing 1 ! set_option -top_module "MAM_D" ! ! #map options ! set_option -frequency 0.000 ! set_option -fanout_limit 100 ! set_option -disable_io_insertion 0 ! set_option -pipe 0 ! set_option -retiming 0 ! ! #simulation options ! set_option -write_verilog 0 ! set_option -write_vhdl 0 ! ! #automatic place and route (vendor) options ! set_option -write_apr_constraint 1 ! ! #set result format/file last ! project -result_file "MAM_D/rev_1.edf" ! ! ! #implementation: "MAM_D_P" ! impl -add MAM_D_P ! ! #device options ! set_option -technology VIRTEX2 ! set_option -part XC2V250 ! set_option -package CS144 ! set_option -speed_grade -5 ! ! #compilation/mapping options ! set_option -default_enum_encoding default ! set_option -symbolic_fsm_compiler 1 ! set_option -resource_sharing 1 ! set_option -top_module "MAM_D_P" ! ! #map options ! set_option -frequency 0.000 ! set_option -fanout_limit 100 ! set_option -disable_io_insertion 0 ! set_option -pipe 0 ! set_option -retiming 0 ! ! #simulation options ! set_option -write_verilog 0 ! set_option -write_vhdl 0 ! ! #automatic place and route (vendor) options ! set_option -write_apr_constraint 1 ! ! #set result format/file last ! project -result_file "MAM_D_P/rev_1.edf" ! ! ! #implementation: "Latch_D" ! impl -add Latch_D ! ! #device options ! set_option -technology VIRTEX2 ! set_option -part XC2V250 ! set_option -package CS144 ! set_option -speed_grade -5 ! ! #compilation/mapping options ! set_option -default_enum_encoding default ! set_option -symbolic_fsm_compiler 1 ! set_option -resource_sharing 1 ! set_option -top_module "Latch_D" ! ! #map options ! set_option -frequency 0.000 ! set_option -fanout_limit 100 ! set_option -disable_io_insertion 0 ! set_option -pipe 0 ! set_option -retiming 0 ! ! #simulation options ! set_option -write_verilog 0 ! set_option -write_vhdl 0 ! ! #automatic place and route (vendor) options ! set_option -write_apr_constraint 1 ! ! #set result format/file last ! project -result_file "Latch_D/rev_1.edf" ! ! ! #implementation: "MUX_RAM" ! impl -add MUX_RAM ! ! #device options ! set_option -technology VIRTEX2 ! set_option -part XC2V250 ! set_option -package CS144 ! set_option -speed_grade -5 ! ! #compilation/mapping options ! set_option -default_enum_encoding default ! set_option -symbolic_fsm_compiler 1 ! set_option -resource_sharing 1 ! set_option -top_module "MUX_RAM" ! ! #map options ! set_option -frequency 0.000 ! set_option -fanout_limit 100 ! set_option -disable_io_insertion 0 ! set_option -pipe 0 ! set_option -retiming 0 ! ! #simulation options ! set_option -write_verilog 0 ! set_option -write_vhdl 0 ! ! #automatic place and route (vendor) options ! set_option -write_apr_constraint 1 ! ! #set result format/file last ! project -result_file "MUX_RAM/rev_1.edf" ! ! ! #implementation: "DEMUX_PP" ! impl -add DEMUX_PP #device options *************** *** 104,108 **** set_option -symbolic_fsm_compiler 1 set_option -resource_sharing 1 ! set_option -top_module "MUX_AD" #map options --- 369,373 ---- set_option -symbolic_fsm_compiler 1 set_option -resource_sharing 1 ! set_option -top_module "DEMUX_PP" #map options *************** *** 121,124 **** #set result format/file last ! project -result_file "MUX_AD/MUX_AD_rtl.edf" ! impl -active "MUX_AD" --- 386,455 ---- #set result format/file last ! project -result_file "DEMUX_PP/rev_1.edf" ! ! ! #implementation: "UpCounter" ! impl -add UpCounter ! ! #device options ! set_option -technology VIRTEX2 ! set_option -part XC2V250 ! set_option -package CS144 ! set_option -speed_grade -5 ! ! #compilation/mapping options ! set_option -default_enum_encoding default ! set_option -symbolic_fsm_compiler 1 ! set_option -resource_sharing 1 ! set_option -top_module "UpCounter" ! ! #map options ! set_option -frequency 100.000 ! set_option -fanout_limit 100 ! set_option -disable_io_insertion 0 ! set_option -pipe 0 ! set_option -retiming 0 ! ! #simulation options ! set_option -write_verilog 0 ! set_option -write_vhdl 0 ! ! #automatic place and route (vendor) options ! set_option -write_apr_constraint 1 ! ! #set result format/file last ! project -result_file "UpCounter/rev_1.edf" ! ! ! #implementation: "Datapath" ! impl -add Datapath ! ! #device options ! set_option -technology VIRTEX ! set_option -part XCV200 ! set_option -package PQ240 ! set_option -speed_grade -6 ! ! #compilation/mapping options ! set_option -default_enum_encoding onehot ! set_option -symbolic_fsm_compiler 1 ! set_option -resource_sharing 1 ! set_option -top_module "Datapath" ! ! #map options ! set_option -frequency 80.000 ! set_option -fanout_limit 100 ! set_option -disable_io_insertion 0 ! set_option -pipe 0 ! set_option -retiming 0 ! ! #simulation options ! set_option -write_verilog 0 ! set_option -write_vhdl 0 ! ! #automatic place and route (vendor) options ! set_option -write_apr_constraint 1 ! ! #set result format/file last ! project -result_file "Datapath/rev_1.edf" ! impl -active "Datapath" |
|
From: Johann G. <han...@us...> - 2003-04-05 10:01:02
|
Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv6012/src
Modified Files:
MUX_AD_rtl.vhd
Log Message:
Added Synplify synthesis directory and a project.
Changed MUX_AD to actually use Join_MinMax and Join_Avg.
Index: MUX_AD_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MUX_AD_rtl.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** MUX_AD_rtl.vhd 10 Mar 2003 14:40:24 -0000 1.2
--- MUX_AD_rtl.vhd 5 Apr 2003 10:00:58 -0000 1.3
***************
*** 40,75 ****
architecture rtl of MUX_AD is
begin -- rtl
! -- purpose: Select which data packet is stored in the RAM word
-- type : combinational
! -- inputs : MAAM_i,Min1_i,Avg1_i,Max1_i,Min2_i,Avg2_i,Max2_i,
! -- Min3_i,Avg3_i,Max3_i,Min4_i,Avg4_i,Max4_i,MinD_i,MaxD_i
-- outputs: RAM_o
! MUX: process (MAAM_i,
! Min1_i,Avg1_i,Max1_i,
! Min2_i,Avg2_i,Max2_i,
! Min3_i,Avg3_i,Max3_i,
! Min4_i,Avg4_i,Max4_i,
! MinD_i,MaxD_i)
begin -- process MUX
case MAAM_i is
! when MAAM_Min => RAM_o( AnalogWidth-1 downto 0) <= Min1_i;
! RAM_o( 2*AnalogWidth-1 downto AnalogWidth) <= Min2_i;
! RAM_o( 3*AnalogWidth-1 downto 2*AnalogWidth) <= Min3_i;
! RAM_o( 4*AnalogWidth-1 downto 3*AnalogWidth) <= Min4_i;
! RAM_o(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth) <= MinD_i;
! when MAAM_Avg1 => RAM_o( AverageWidth-1 downto 0) <= Avg1_i;
! RAM_o( 2*AverageWidth-1 downto AverageWidth) <= Avg2_i;
! when MAAM_Avg2 => RAM_o( AverageWidth-1 downto 0) <= Avg3_i;
! RAM_o( 2*AverageWidth-1 downto AverageWidth) <= Avg4_i;
! -- MAAM_Max:
! when others => RAM_o( AnalogWidth-1 downto 0) <= Max1_i;
! RAM_o( 2*AnalogWidth-1 downto AnalogWidth) <= Max2_i;
! RAM_o( 3*AnalogWidth-1 downto 2*AnalogWidth) <= Max3_i;
! RAM_o( 4*AnalogWidth-1 downto 3*AnalogWidth) <= Max4_i;
! RAM_o(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth) <= MaxD_i;
end case;
end process MUX;
end rtl;
--- 40,162 ----
architecture rtl of MUX_AD is
+ component Join_Avg is
+ generic (
+ AverageWidth : Integer := 36; -- width of average data
+ RAM_Width : Integer := 72); -- width of data bus to RAM
+ port (
+ Avg1_i : in std_logic_vector(AverageWidth-1 downto 0); -- data from first average channel
+ Avg2_i : in std_logic_vector(AverageWidth-1 downto 0); -- data from second average channel
+ Out_o : out std_logic_vector(RAM_Width-1 downto 0)); -- data path to RAM
+ end component;
+
+ component Join_MinMax is
+ generic (
+ AnalogWidth : Integer := 10; -- width of analog channels
+ DigitalWidth : Integer := 32; -- width of digital input
+ RAM_Width : Integer := 72); -- width of data bus to RAM
+ port (
+ Ch1_i : in std_logic_vector(AnalogWidth-1 downto 0); -- data from channel 1
+ Ch2_i : in std_logic_vector(AnalogWidth-1 downto 0); -- data from channel 2
+ Ch3_i : in std_logic_vector(AnalogWidth-1 downto 0); -- data from channel 3
+ Ch4_i : in std_logic_vector(AnalogWidth-1 downto 0); -- data from channel 4
+ Dig_i : in std_logic_vector(DigitalWidth-1 downto 0); -- data from digital inputs
+ Out_o : out std_logic_vector(RAM_Width-1 downto 0)); -- data path to RAM
+ end component;
+
+ signal s_Min : std_logic_vector(RAM_Width-1 downto 0);
+ signal s_Avg1 : std_logic_vector(RAM_Width-1 downto 0);
+ signal s_Avg2 : std_logic_vector(RAM_Width-1 downto 0);
+ signal s_Max : std_logic_vector(RAM_Width-1 downto 0);
begin -- rtl
! i_Min : Join_MinMax
! generic map (
! AnalogWidth => AnalogWidth,
! DigitalWidth => DigitalWidth,
! RAM_Width => RAM_Width)
! port map (
! Ch1_i => Min1_i,
! Ch2_i => Min2_i,
! Ch3_i => Min3_i,
! Ch4_i => Min4_i,
! Dig_i => MinD_i,
! Out_o => s_Min);
!
! i_Avg1 : Join_Avg
! generic map (
! AverageWidth => AverageWidth,
! RAM_Width => RAM_Width)
! port map (
! Avg1_i => Avg1_i,
! Avg2_i => Avg2_i,
! Out_o => s_Avg1);
!
! i_Avg2 : Join_Avg
! generic map (
! AverageWidth => AverageWidth,
! RAM_Width => RAM_Width)
! port map (
! Avg1_i => Avg3_i,
! Avg2_i => Avg4_i,
! Out_o => s_Avg2);
!
! i_Max : Join_MinMax
! generic map (
! AnalogWidth => AnalogWidth,
! DigitalWidth => DigitalWidth,
! RAM_Width => RAM_Width)
! port map (
! Ch1_i => Max1_i,
! Ch2_i => Max2_i,
! Ch3_i => Max3_i,
! Ch4_i => Max4_i,
! Dig_i => MaxD_i,
! Out_o => s_Max);
!
! -- purpose: select which data packet is stored in the RAM word
-- type : combinational
! -- inputs : MAAM_i,s_Min,s_Avg1,s_Avg2,s_Max
-- outputs: RAM_o
! MUX: process (MAAM_i,s_Min,s_Avg1,s_Avg2,s_Max)
begin -- process MUX
case MAAM_i is
! when MAAM_Min => RAM_o <= s_Min;
! when MAAM_Avg1 => RAM_o <= s_Avg1;
! when MAAM_Avg2 => RAM_o <= s_Avg2;
! when others => RAM_o <= s_Max;
end case;
end process MUX;
+
+
+ -- -- purpose: Select which data packet is stored in the RAM word
+ -- -- type : combinational
+ -- -- inputs : MAAM_i,Min1_i,Avg1_i,Max1_i,Min2_i,Avg2_i,Max2_i,
+ -- -- Min3_i,Avg3_i,Max3_i,Min4_i,Avg4_i,Max4_i,MinD_i,MaxD_i
+ -- -- outputs: RAM_o
+ -- MUX: process (MAAM_i,
+ -- Min1_i,Avg1_i,Max1_i,
+ -- Min2_i,Avg2_i,Max2_i,
+ -- Min3_i,Avg3_i,Max3_i,
+ -- Min4_i,Avg4_i,Max4_i,
+ -- MinD_i,MaxD_i)
+ -- begin -- process MUX
+ -- case MAAM_i is
+ -- when MAAM_Min => RAM_o( AnalogWidth-1 downto 0) <= Min1_i;
+ -- RAM_o( 2*AnalogWidth-1 downto AnalogWidth) <= Min2_i;
+ -- RAM_o( 3*AnalogWidth-1 downto 2*AnalogWidth) <= Min3_i;
+ -- RAM_o( 4*AnalogWidth-1 downto 3*AnalogWidth) <= Min4_i;
+ -- RAM_o(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth) <= MinD_i;
+ -- when MAAM_Avg1 => RAM_o( AverageWidth-1 downto 0) <= Avg1_i;
+ -- RAM_o( 2*AverageWidth-1 downto AverageWidth) <= Avg2_i;
+ -- when MAAM_Avg2 => RAM_o( AverageWidth-1 downto 0) <= Avg3_i;
+ -- RAM_o( 2*AverageWidth-1 downto AverageWidth) <= Avg4_i;
+ -- -- MAAM_Max:
+ -- when others => RAM_o( AnalogWidth-1 downto 0) <= Max1_i;
+ -- RAM_o( 2*AnalogWidth-1 downto AnalogWidth) <= Max2_i;
+ -- RAM_o( 3*AnalogWidth-1 downto 2*AnalogWidth) <= Max3_i;
+ -- RAM_o( 4*AnalogWidth-1 downto 3*AnalogWidth) <= Max4_i;
+ -- RAM_o(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth) <= MaxD_i;
+ -- end case;
+ -- end process MUX;
end rtl;
|
|
From: Johann G. <han...@us...> - 2003-04-05 10:01:01
|
Update of /cvsroot/dso/FPGA/Synplify
In directory sc8-pr-cvs1:/tmp/cvs-serv6012/Synplify
Added Files:
project.prd project.prj
Log Message:
Added Synplify synthesis directory and a project.
Changed MUX_AD to actually use Join_MinMax and Join_Avg.
--- NEW FILE: project.prd ---
#-- Synplicity, Inc.
#-- Version 7.0.3
#-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prd
#-- Written on Sat Apr 5 11:53:16 2003
#
### Watch Implementation type ###
#
watch_impl -active
#
### Watch Implementation properties ###
#
watch_prop -clear { MUX_AD Part } { MUX_AD Total Luts } { MUX_AD I/O primitives }
--- NEW FILE: project.prj ---
#-- Synplicity, Inc.
#-- Version 7.0.3
#-- Project file /home/hansi/Projekte/DSO/src/FPGA/FPGA/Synplify/project.prj
#-- Written on Sat Apr 5 11:53:16 2003
#add_file options
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/types_p.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Reg_N_Load_8_.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Reg_N_Load_8_rtl.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Avg_A_.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Avg_A_rtl.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/DownCounter_.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/DownCounter_rtl.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/CountDown_.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/CountDown_struc.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Join_MinMax_.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Join_MinMax_struc.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Join_Avg_.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/Join_Avg_struc.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_AD_.vhd"
add_file -vhdl -lib work "/home/hansi/Projekte/DSO/src/FPGA/FPGA/src/MUX_AD_rtl.vhd"
#reporting options
#implementation: "Reg_N_Load_8"
impl -add Reg_N_Load_8
#device options
set_option -technology VIRTEX2
set_option -part XC2V250
set_option -package CS144
set_option -speed_grade -5
#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -top_module "Reg_N_Load_8"
#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "Reg_N_Load_8/rev_1.edf"
#implementation: "CountDown"
impl -add CountDown
#device options
set_option -technology VIRTEX2
set_option -part XC2V250
set_option -package CS144
set_option -speed_grade -5
#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -top_module "CountDown"
#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "CountDown/MUX_AD_rtl.edf"
#implementation: "MUX_AD"
impl -add MUX_AD
#device options
set_option -technology VIRTEX2
set_option -part XC2V250
set_option -package CS144
set_option -speed_grade -5
#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -top_module "MUX_AD"
#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "MUX_AD/MUX_AD_rtl.edf"
impl -active "MUX_AD"
|
|
From: Johann G. <han...@us...> - 2003-04-05 09:53:39
|
Update of /cvsroot/dso/FPGA/Synplify In directory sc8-pr-cvs1:/tmp/cvs-serv4019/Synplify Log Message: Directory /cvsroot/dso/FPGA/Synplify added to the repository |
|
From: Johann G. <han...@us...> - 2003-04-04 09:32:32
|
Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv1367/src
Modified Files:
Reg_N_Load_8_rtl.vhd
Log Message:
Updated TODO and wrote lots of comments to src/Reg_N_Load_8_rtl.vhd.
Index: Reg_N_Load_8_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Reg_N_Load_8_rtl.vhd,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** Reg_N_Load_8_rtl.vhd 4 Apr 2003 09:21:00 -0000 1.4
--- Reg_N_Load_8_rtl.vhd 4 Apr 2003 09:32:28 -0000 1.5
***************
*** 2,5 ****
--- 2,6 ----
--
-- Author: Gerald Zach
+ -- Modified for synthesis by Johann Glaser
--
-- Filename: Reg_N_Load_8_rtl.vhd
***************
*** 71,74 ****
--- 72,88 ----
Out_o(OutWidth*8-8-1 downto 0) <= Data(OutWidth*8-8-1 downto 0);
Out_o(OutWidth*8 -1 downto OutWidth*8-8) <= Data_i;
+ -- To see something really beautiful replace the two lines above
+ -- ('Out_o(OutWidth*8...') with the single line below this comment.
+ -- Additionally you have to change the declaration of the signal
+ -- "Data" to '...OutWidth*8-1 downto ...'. Finally modify the loop
+ -- start index of the "assemble" loop to 'OutWidth-1'.
+ --
+ -- This gives a really beautiful synthesis result. The only drawback
+ -- is that when writing the MSB the _old_ MSB is written to the
+ -- output. Though, there is a latency of 1 write cycle but only for
+ -- the MSB.
+ --
+ -- BTW: Even in the existing version using the above changes doesn't
+ -- influence the synthesis result and gives the correct result.
-- Out_o <= Data;
end if;
***************
*** 79,83 ****
end rtl;
! -- this version is correct but has ugly synthesis results
--
--architecture rtl of Reg_N_Load_8 is
--- 93,97 ----
end rtl;
! -- This version from Gerald Zach is correct but has ugly synthesis results
--
--architecture rtl of Reg_N_Load_8 is
|
|
From: Johann G. <han...@us...> - 2003-04-04 09:32:31
|
Update of /cvsroot/dso/FPGA In directory sc8-pr-cvs1:/tmp/cvs-serv1367 Modified Files: TODO Log Message: Updated TODO and wrote lots of comments to src/Reg_N_Load_8_rtl.vhd. Index: TODO =================================================================== RCS file: /cvsroot/dso/FPGA/TODO,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** TODO 1 Apr 2003 12:28:30 -0000 1.4 --- TODO 4 Apr 2003 09:32:27 -0000 1.5 *************** *** 1,4 **** --- 1,5 ---- - Architectures for DSO, Control, Kernel and Trigger + - Architecture and Entity for Datapath - tb_MAM_A.vhd: line 84: "1=1" -- can be written as "(true)" - tb_Avg_A.vhd: clock and reset are modelled awkwardly *************** *** 13,17 **** - use "En" and "Through" signals in testbenches - update compile.tcl for the new files - - try to get real multiplexers in MUX_uC (instead of AND gates) - - PP_Clk - - MUX_N_1 --- 14,15 ---- |
|
From: Johann G. <han...@us...> - 2003-04-04 09:21:04
|
Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv29795/src
Modified Files:
Reg_N_Load_8_rtl.vhd
Log Message:
Heavily modified src/Reg_N_Load_8_rtl.vhd to get acceptable synthesis results.
Index: Reg_N_Load_8_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Reg_N_Load_8_rtl.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** Reg_N_Load_8_rtl.vhd 3 Apr 2003 14:26:30 -0000 1.3
--- Reg_N_Load_8_rtl.vhd 4 Apr 2003 09:21:00 -0000 1.4
***************
*** 34,60 ****
architecture rtl of Reg_N_Load_8 is
!
begin -- rtl
! -- purpose: synthesis of a (2^N)*8 reload register by 8 bit data words
-- type : sequential
-- inputs : Clk, Reset, Addr_i, Wr_n_i, Data_i
-- outputs: Out_o
p_Reg: process (Clk, Reset)
! variable Data : std_logic_vector(OutWidth*8-1 downto 0) := (others => '0'); -- internal data word synthesis
!
begin -- process p_Reg
! if Reset = '1' then -- asynchronous reset (active low)
! Data := (others => '0');
! Out_o <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if Wr_n_i = '0' then
! Data((conv_integer(Addr_i)+1)*8-1 downto conv_integer(Addr_i)*8) := Data_i;
! if conv_integer(not Addr_i) = 0 then
! Out_o <= Data;
! end if;
end if;
end if;
end process p_Reg;
end rtl;
--- 34,105 ----
architecture rtl of Reg_N_Load_8 is
! signal Data : std_logic_vector(OutWidth*8-8-1 downto 0); -- internal data word assembly except MSB
begin -- rtl
! -- purpose: assembly of a (2^N)*8 reload register by 8 bit data words
-- type : sequential
-- inputs : Clk, Reset, Addr_i, Wr_n_i, Data_i
-- outputs: Out_o
p_Reg: process (Clk, Reset)
! variable i : Integer;
begin -- process p_Reg
! if Reset = '0' then -- asynchronous reset (active low)
! Data <= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if Wr_n_i = '0' then
! assemble: for i in OutWidth-2 downto 0 loop
! if conv_integer(Addr_i)=i then
! Data((i+1)*8-1 downto i*8) <= Data_i;
! end if;
! end loop;
end if;
end if;
end process p_Reg;
+ -- purpose: when Addr=(others => '1') the MSB is stored and all previously
+ -- written bytes including the new MSB are switched to the output
+ -- type : sequential
+ -- inputs : Clk, Reset
+ -- outputs: Out_o
+ p_Out: process (Clk, Reset)
+ begin -- process p_Out
+ if Reset = '0' then -- asynchronous reset (active low)
+ Out_o <= (others => '0');
+ elsif Clk'event and Clk = '1' then -- rising clock edge
+ if Wr_n_i = '0' then
+ if conv_integer(not Addr_i) = 0 then
+ Out_o(OutWidth*8-8-1 downto 0) <= Data(OutWidth*8-8-1 downto 0);
+ Out_o(OutWidth*8 -1 downto OutWidth*8-8) <= Data_i;
+ -- Out_o <= Data;
+ end if;
+ end if;
+ end if;
+ end process p_Out;
+
end rtl;
+
+ -- this version is correct but has ugly synthesis results
+ --
+ --architecture rtl of Reg_N_Load_8 is
+ --begin -- rtl
+ -- -- purpose: synthesis of a (2^N)*8 reload register by 8 bit data words
+ -- -- type : sequential
+ -- -- inputs : Clk, Reset, Addr_i, Wr_n_i, Data_i
+ -- -- outputs: Out_o
+ -- p_Reg: process (Clk, Reset)
+ -- variable Data : std_logic_vector(OutWidth*8-1 downto 0) := (others => '0'); -- internal data word synthesis
+ -- begin -- process p_Reg
+ -- if Reset = '1' then -- asynchronous reset (active low)
+ -- Data := (others => '0');
+ -- Out_o <= (others => '0');
+ -- elsif Clk'event and Clk = '1' then -- rising clock edge
+ -- if Wr_n_i = '0' then
+ -- Data((conv_integer(Addr_i)+1)*8-1 downto conv_integer(Addr_i)*8) := Data_i;
+ -- if conv_integer(not Addr_i) = 0 then
+ -- Out_o <= Data;
+ -- end if;
+ -- end if;
+ -- end if;
+ -- end process p_Reg;
+ --end rtl;
+
|
|
From: Gerald Z. <ri...@us...> - 2003-04-03 14:26:34
|
Update of /cvsroot/dso/FPGA/tb
In directory sc8-pr-cvs1:/tmp/cvs-serv28033/tb
Added Files:
tb_CountDown.vhd tb_DownCounter.vhd tb_Reg_N_Load_8.vhd
Log Message:
testbenches for CountDown, DownCounter & Reg_N_Load_8 added
tests & components ok, but not "assert -> warning " included yet
UpCounter.vhd corrected
--- NEW FILE: tb_CountDown.vhd ---
-------------------------------------------------------------------------------
--
-- Author: Gerald Zach
--
-- Filename: tb_CountDown.vhd
--
-- Date of Creation: 03-04-2003
--
-- Description: Testbench for CountDown
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2003 Gerald Zach
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.all;
-----------------------------ENTITY DECLARATION--------------------------------
entity tb_CountDown is
generic (
AddrWidth : integer := 2; -- # of address lines (2^AddrWith*8 = counter width)
CountWidth : integer := 4); -- = 2^AddrWidth
end tb_CountDown;
architecture sim of tb_CountDown is
signal ClkReg : std_logic := '0';
signal ClkCntr : std_logic := '0';
signal Data : std_logic_vector(7 downto 0) := (others => '0');
signal Addr : std_logic_vector(AddrWidth-1 downto 0) := (others => '0');
signal Wr : std_logic := '1';
signal Reset : std_logic := '0';
signal Reload : std_logic := '0';
signal Dec : std_logic := '0';
signal Zero : std_logic;
component CountDown
generic (AddrWidth : integer := 2; -- # of address lines (2^Addr*8 = counter width)
CountWidth : integer := 4); -- =2^AddrWidth
port (Data_i : in std_logic_vector(7 downto 0); -- reload word 8 bit
Addr_i : in std_logic_vector(AddrWidth-1 downto 0); -- address select
Wr_n_i : in std_logic; -- write signal (active low)
ClkReg : in std_logic; -- clock for Register
ClkCntr : in std_logic; -- clock for Counter
Reset : in std_logic;
Reload_i : in std_logic; -- reload signal
Dec_i : in std_logic; -- decrement signal
Zero_o : out std_logic); -- goes high when counter reaches 0
end component;
begin -- sim
i_CountDown: CountDown
generic map (
AddrWidth => AddrWidth,
CountWidth => CountWidth)
port map (
Data_i => Data,
Addr_i => Addr,
Wr_n_i => Wr,
ClkReg => ClkReg,
ClkCntr => ClkCntr,
Reset => Reset,
Reload_i => Reload,
Dec_i => Dec,
Zero_o => Zero);
-- purpose: generate clock for counter
-- type : combinational
-- inputs :
-- outputs: ClkCntr
p_ClkCntr: process
begin -- process p_ClkCntr
ClkCntr <= not ClkCntr;
wait for 20 ns;
end process p_ClkCntr;
-- purpose: clock for loading Register
-- type : combinational
-- inputs :
-- outputs: ClkReg
p_ClkReg: process
begin -- process p_ClkReg
ClkReg <= not ClkReg;
wait for 50 ns;
end process p_ClkReg;
-- purpose: testing CountDown
-- type : combinational
-- inputs :
-- outputs: Addr, Data, Wr, Reload, Dec, Reset
p_test: process
begin -- process testing CountDown
Reset <= '1';
wait for 30 ns;
Reset <= '0';
wait for 10 ns;
Addr <= "00";
Data <= "00000101";
--Data <= "10101010";
wait for 20 ns;
Wr <= '0';
wait for 200 ns;
Wr <= '1';
wait for 20 ns;
Addr <= "01";
Data <= "00000000";
--Data <= "11001100";
wait for 20 ns;
Wr <= '0';
wait for 200 ns;
Wr <= '1';
wait for 20 ns;
Addr <= "10";
Data <= "00000000";
--Data <= "11101110";
wait for 20 ns;
Wr <= '0';
wait for 200 ns;
Wr <= '1';
wait for 20 ns;
Addr <= "11";
Data <= "00000000";
--Data <= "11110000";
wait for 20 ns;
Wr <= '0';
wait for 200 ns;
Wr <= '1';
wait for 20 ns;
Reload <= '1';
wait for 100 ns;
Reload <= '0';
wait for 70 ns;
Dec <= '1';
wait for 1000 ns;
Dec <= '0';
end process p_test;
end sim;
--- NEW FILE: tb_DownCounter.vhd ---
-------------------------------------------------------------------------------
--
-- Author: Gerald Zach
--
-- Filename: tb_DownCounter.vhd
--
-- Date of Creation: 03-04-2003
--
-- Description: Testbench for DownCounter
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2003 Gerald Zach
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.all;
-----------------------------ENTITY DECLARATION--------------------------------
entity tb_DownCounter is
generic (
N : integer := 32); -- counter width
end tb_DownCounter;
architecture sim of tb_DownCounter is
signal ClkCntr : std_logic := '0';
signal Data : std_logic_vector(N-1 downto 0) := (others => '0');
signal Reset : std_logic := '0';
signal Reload : std_logic := '0';
signal Dec : std_logic := '0';
signal Zero : std_logic;
component DownCounter
generic (N : integer); -- count word width
port (In_i : in std_logic_vector(N-1 downto 0);
Reload_i : in std_logic; -- reload signal
Dec_i : in std_logic; -- decrement counter signal
Clk : in std_logic;
Reset : in std_logic;
Zero_o : out std_logic); -- goes to '1' when counter is zero
end component;
begin -- sim
i_DownCounter: DownCounter
generic map (
N => N)
port map (
In_i => Data,
Clk => ClkCntr,
Reset => Reset,
Reload_i => Reload,
Dec_i => Dec,
Zero_o => Zero);
-- purpose: generate clock for counter
-- type : combinational
-- inputs :
-- outputs: ClkCntr
p_ClkCntr: process
begin -- process p_ClkCntr
ClkCntr <= not ClkCntr;
wait for 20 ns;
end process p_ClkCntr;
-- purpose: testing DownCounter
-- type : combinational
-- inputs :
-- outputs: Data, Reload, Dec, Reset
p_test: process
begin -- process testing DownCounter
Reset <= '1';
wait for 30 ns;
Reset <= '0';
Data <= conv_std_logic_vector(5,N);
wait for 10 ns;
Reload <= '1';
wait for 100 ns;
Reload <= '0';
wait for 70 ns;
Dec <= '1';
wait for 1000 ns;
Dec <= '0';
end process p_test;
end sim;
--- NEW FILE: tb_Reg_N_Load_8.vhd ---
-------------------------------------------------------------------------------
--
-- Author: Gerald Zach
--
-- Filename: tb_Reg_N_Load_8.vhd
--
-- Date of Creation: 03-04-2003
--
-- Description: Testbench for Reg_N_Load_8
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2003 Gerald Zach
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.all;
-----------------------------ENTITY DECLARATION--------------------------------
entity tb_Reg_N_Load_8 is
generic (
AddrWidth : integer := 2; -- # of address lines (2^AddrWith*8 = counter width)
OutWidth : integer := 4); -- = 2^AddrWidth
end tb_Reg_N_Load_8;
architecture sim of tb_Reg_N_Load_8 is
signal ClkReg : std_logic := '0';
signal Data : std_logic_vector(7 downto 0) := (others => '0');
signal Addr : std_logic_vector(AddrWidth-1 downto 0) := (others => '0');
signal Wr : std_logic := '1';
signal Reset : std_logic := '0';
signal OutReg : std_logic_vector(OutWidth*8-1 downto 0) := (others => '0');
component Reg_N_Load_8
generic (AddrWidth : integer := 2; -- number of address select lines (2^AddrWidth*8 = output width)
OutWidth : integer := 4); -- 2^AddrWidth
port (Data_i : in std_logic_vector(7 downto 0); -- input data
Wr_n_i : in std_logic; -- write signal (active low)
Addr_i : in std_logic_vector(AddrWidth-1 downto 0); -- adressing
Clk : in std_logic;
Reset : in std_logic;
Out_o : out std_logic_vector(8*OutWidth-1 downto 0)); -- full width output word
end component;
begin -- sim
i_Reg: Reg_N_Load_8
generic map (
AddrWidth => AddrWidth,
OutWidth => OutWidth)
port map (
Data_i => Data,
Addr_i => Addr,
Wr_n_i => Wr,
Clk => ClkReg,
Reset => Reset,
Out_o => OutReg);
-- purpose: clock for loading Register
-- type : combinational
-- inputs :
-- outputs: ClkReg
p_ClkReg: process
begin -- process p_ClkReg
ClkReg <= not ClkReg;
wait for 50 ns;
end process p_ClkReg;
-- purpose: testing Reg_N_Load_8
-- type : combinational
-- inputs :
-- outputs: Addr, Data, Wr, Reload, Dec, Reset
p_test: process
begin -- process testing CountDown
Reset <= '1';
wait for 30 ns;
Reset <= '0';
wait for 10 ns;
Addr <= "00";
--Data <= "00000101";
Data <= "10101010";
wait for 20 ns;
Wr <= '0';
wait for 200 ns;
Wr <= '1';
wait for 20 ns;
Addr <= "01";
--Data <= "00000000";
Data <= "11001100";
wait for 20 ns;
Wr <= '0';
wait for 200 ns;
Wr <= '1';
wait for 20 ns;
Addr <= "10";
--Data <= "00000000";
Data <= "11101110";
wait for 20 ns;
Wr <= '0';
wait for 200 ns;
Wr <= '1';
wait for 20 ns;
Addr <= "11";
--Data <= "00000000";
Data <= "11110000";
wait for 20 ns;
Wr <= '0';
wait for 200 ns;
Wr <= '1';
wait for 20 ns;
wait for 1000 ns;
end process p_test;
end sim;
|
|
From: Gerald Z. <ri...@us...> - 2003-04-03 14:26:33
|
Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv28033/src
Modified Files:
CountDown_struc.vhd DownCounter_rtl.vhd Reg_N_Load_8_.vhd
Reg_N_Load_8_rtl.vhd UpCounter_rtl.vhd
Log Message:
testbenches for CountDown, DownCounter & Reg_N_Load_8 added
tests & components ok, but not "assert -> warning " included yet
UpCounter.vhd corrected
Index: CountDown_struc.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/CountDown_struc.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** CountDown_struc.vhd 1 Apr 2003 12:16:23 -0000 1.1
--- CountDown_struc.vhd 3 Apr 2003 14:26:29 -0000 1.2
***************
*** 75,79 ****
i_Count: DownCounter
generic map (
! N => CountWidth)
port map (
In_i => Con,
--- 75,79 ----
i_Count: DownCounter
generic map (
! N => CountWidth*8)
port map (
In_i => Con,
Index: DownCounter_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/DownCounter_rtl.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** DownCounter_rtl.vhd 1 Apr 2003 10:11:25 -0000 1.1
--- DownCounter_rtl.vhd 3 Apr 2003 14:26:29 -0000 1.2
***************
*** 31,35 ****
library IEEE;
use IEEE.std_logic_1164.all;
! use IEEE.std_logic_signed.all;
architecture rtl of DownCounter is
--- 31,35 ----
library IEEE;
use IEEE.std_logic_1164.all;
! use IEEE.std_logic_arith.all;
architecture rtl of DownCounter is
***************
*** 42,52 ****
-- outputs: Zero_o
p_DownCounter: process (Clk, Reset)
! variable Count : std_logic_vector(N-1 downto 0) := (others => '0'); -- counter state
begin -- process p_DownCounter
! if Reset = '0' then -- asynchronous reset (active low)
! Count:= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if Reload_i='1' then
! Count:=In_i;
elsif Dec_i='1' then
Count:=Count-1;
--- 42,52 ----
-- outputs: Zero_o
p_DownCounter: process (Clk, Reset)
! variable Count :integer :=0; -- counter state
begin -- process p_DownCounter
! if Reset = '1' then -- asynchronous reset (active low)
! Count:= 0;
elsif Clk'event and Clk = '1' then -- rising clock edge
if Reload_i='1' then
! Count:=conv_integer(In_i);
elsif Dec_i='1' then
Count:=Count-1;
Index: Reg_N_Load_8_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Reg_N_Load_8_.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** Reg_N_Load_8_.vhd 1 Apr 2003 12:19:16 -0000 1.3
--- Reg_N_Load_8_.vhd 3 Apr 2003 14:26:30 -0000 1.4
***************
*** 7,11 ****
-- Date of Creation: 01-04-2003
--
! -- Description: presatable upward counter
--
-------------------------------------------------------------------------------
--- 7,11 ----
-- Date of Creation: 01-04-2003
--
! -- Description: N bit register loaded by 8bit words
--
-------------------------------------------------------------------------------
***************
*** 46,50 ****
Clk : in std_logic;
Reset : in std_logic;
! Out_o : out std_logic_vector(4*OutWidth-1 downto 0)); -- full width output word
end Reg_N_Load_8;
--- 46,50 ----
Clk : in std_logic;
Reset : in std_logic;
! Out_o : out std_logic_vector(8*OutWidth-1 downto 0)); -- full width output word
end Reg_N_Load_8;
Index: Reg_N_Load_8_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Reg_N_Load_8_rtl.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** Reg_N_Load_8_rtl.vhd 1 Apr 2003 12:19:16 -0000 1.2
--- Reg_N_Load_8_rtl.vhd 3 Apr 2003 14:26:30 -0000 1.3
***************
*** 7,11 ****
-- Date of Creation: 01-04-2003
--
! -- Description: presatable upward counter - rtl design
--
-------------------------------------------------------------------------------
--- 7,11 ----
-- Date of Creation: 01-04-2003
--
! -- Description: N bit register loaded by 8bit words - rtl design
--
-------------------------------------------------------------------------------
***************
*** 31,35 ****
library IEEE;
use IEEE.std_logic_1164.all;
! use IEEE.std_logic_signed.all;
architecture rtl of Reg_N_Load_8 is
--- 31,35 ----
library IEEE;
use IEEE.std_logic_1164.all;
! use IEEE.std_logic_unsigned.all;
architecture rtl of Reg_N_Load_8 is
***************
*** 45,49 ****
begin -- process p_Reg
! if Reset = '0' then -- asynchronous reset (active low)
Data := (others => '0');
Out_o <= (others => '0');
--- 45,49 ----
begin -- process p_Reg
! if Reset = '1' then -- asynchronous reset (active low)
Data := (others => '0');
Out_o <= (others => '0');
***************
*** 55,59 ****
end if;
end if;
-
end if;
end process p_Reg;
--- 55,58 ----
Index: UpCounter_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/UpCounter_rtl.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** UpCounter_rtl.vhd 1 Apr 2003 10:11:25 -0000 1.1
--- UpCounter_rtl.vhd 3 Apr 2003 14:26:30 -0000 1.2
***************
*** 31,35 ****
library IEEE;
use IEEE.std_logic_1164.all;
! use IEEE.std_logic_signed.all;
architecture rtl of UpCounter is
--- 31,35 ----
library IEEE;
use IEEE.std_logic_1164.all;
! use IEEE.std_logic_arith.all;
architecture rtl of UpCounter is
***************
*** 42,57 ****
-- outputs: Out_o
p_UpCounter: process (Clk, Reset)
! variable Count : std_logic_vector(N-1 downto 0) := (others => '0'); -- counter state
begin -- process p_DownCounter
! if Reset = '0' then -- asynchronous reset (active low)
! Count:= (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
if Reload_i='1' then
! Count:=In_i;
elsif Inc_i='1' then
Count:=Count+1;
end if;
end if;
! Out_o <= Count;
end process p_UpCounter;
--- 42,57 ----
-- outputs: Out_o
p_UpCounter: process (Clk, Reset)
! variable Count : integer :=0; -- counter state
begin -- process p_DownCounter
! if Reset = '1' then -- asynchronous reset (active low)
! Count:= 0;
elsif Clk'event and Clk = '1' then -- rising clock edge
if Reload_i='1' then
! Count:=conv_integer(In_i);
elsif Inc_i='1' then
Count:=Count+1;
end if;
end if;
! Out_o <= conv_std_logic_vector(Count,N);
end process p_UpCounter;
|
|
From: Johann G. <han...@us...> - 2003-04-01 12:28:33
|
Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv12427/src
Modified Files:
MUX_uC_.vhd MUX_uC_rtl.vhd
Log Message:
Corrections in MUX_uC.
Index: MUX_uC_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MUX_uC_.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** MUX_uC_.vhd 1 Apr 2003 12:15:56 -0000 1.1
--- MUX_uC_.vhd 1 Apr 2003 12:28:30 -0000 1.2
***************
*** 47,49 ****
Select_i : in std_logic_vector( 3 downto 0)); -- select the section from the data path
! end MUX_4_N;
--- 47,49 ----
Select_i : in std_logic_vector( 3 downto 0)); -- select the section from the data path
! end MUX_uC;
Index: MUX_uC_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/MUX_uC_rtl.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** MUX_uC_rtl.vhd 1 Apr 2003 12:15:57 -0000 1.1
--- MUX_uC_rtl.vhd 1 Apr 2003 12:28:30 -0000 1.2
***************
*** 43,49 ****
-- purpose: select one out of the 4 inputs depending on Select_i's value
-- type : combinational
! -- inputs : Select_i,In1_i,In2_i,In3_i,In4_i
-- outputs: Out_o
! MUX: process (Select_i,In1_i,In2_i,In3_i,In4_i)
begin -- process MUX
case Select_i is
--- 43,49 ----
-- purpose: select one out of the 4 inputs depending on Select_i's value
-- type : combinational
! -- inputs : Select_i,PP_i
-- outputs: Out_o
! MUX: process (Select_i,PP_i )
begin -- process MUX
case Select_i is
***************
*** 55,59 ****
when "0101" => uC_o <= PP_i(47 downto 40);
when "0110" => uC_o <= PP_i(55 downto 48);
! when "0111" => uC_o <= PP_i(64 downto 56);
when "1000" => uC_o <= PP_i(71 downto 64);
when others => uC_o <= (others => '0');
--- 55,59 ----
when "0101" => uC_o <= PP_i(47 downto 40);
when "0110" => uC_o <= PP_i(55 downto 48);
! when "0111" => uC_o <= PP_i(63 downto 56);
when "1000" => uC_o <= PP_i(71 downto 64);
when others => uC_o <= (others => '0');
|
|
From: Johann G. <han...@us...> - 2003-04-01 12:28:33
|
Update of /cvsroot/dso/FPGA In directory sc8-pr-cvs1:/tmp/cvs-serv12427 Modified Files: TODO Log Message: Corrections in MUX_uC. Index: TODO =================================================================== RCS file: /cvsroot/dso/FPGA/TODO,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** TODO 1 Apr 2003 11:53:34 -0000 1.3 --- TODO 1 Apr 2003 12:28:30 -0000 1.4 *************** *** 12,13 **** --- 12,17 ---- - adjust all testbenches to the changed architectures - use "En" and "Through" signals in testbenches + - update compile.tcl for the new files + - try to get real multiplexers in MUX_uC (instead of AND gates) + - PP_Clk + - MUX_N_1 |
|
From: Gerald Z. <ri...@us...> - 2003-04-01 12:19:21
|
Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv9044/src
Modified Files:
Reg_N_Load_8_.vhd Reg_N_Load_8_rtl.vhd
Log Message:
Index: Reg_N_Load_8_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Reg_N_Load_8_.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** Reg_N_Load_8_.vhd 1 Apr 2003 12:16:23 -0000 1.2
--- Reg_N_Load_8_.vhd 1 Apr 2003 12:19:16 -0000 1.3
***************
*** 43,47 ****
port (Data_i : in std_logic_vector(7 downto 0); -- input data
Wr_n_i : in std_logic; -- write signal (active low)
! Addr_i : in std_logic_vector(N-1 downto 0); -- adressing
Clk : in std_logic;
Reset : in std_logic;
--- 43,47 ----
port (Data_i : in std_logic_vector(7 downto 0); -- input data
Wr_n_i : in std_logic; -- write signal (active low)
! Addr_i : in std_logic_vector(AddrWidth-1 downto 0); -- adressing
Clk : in std_logic;
Reset : in std_logic;
Index: Reg_N_Load_8_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Reg_N_Load_8_rtl.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** Reg_N_Load_8_rtl.vhd 1 Apr 2003 10:11:25 -0000 1.1
--- Reg_N_Load_8_rtl.vhd 1 Apr 2003 12:19:16 -0000 1.2
***************
*** 42,46 ****
-- outputs: Out_o
p_Reg: process (Clk, Reset)
! variable Data : std_logic_vector(N-1 downto 0) := (others => '0'); -- internal data word synthesis
begin -- process p_Reg
--- 42,46 ----
-- outputs: Out_o
p_Reg: process (Clk, Reset)
! variable Data : std_logic_vector(OutWidth*8-1 downto 0) := (others => '0'); -- internal data word synthesis
begin -- process p_Reg
|