[Dso-cvs] FPGA/src DEMUX_PP_.vhd,1.3,1.4 DEMUX_PP_rtl.vhd,1.4,1.5 Datapath_.vhd,1.2,1.3 Datapath_str
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[Dso-cvs] FPGA/src DEMUX_PP_.vhd,1.3,1.4 DEMUX_PP_rtl.vhd,1.4,1.5 Datapath_.vhd,1.2,1.3 Datapath_struc.vhd,1.3,1.4 types_p.vhd,1.3,1.4
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From: Johann G. <han...@us...> - 2003-05-14 08:38:04
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Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv26131/src
Modified Files:
DEMUX_PP_.vhd DEMUX_PP_rtl.vhd Datapath_.vhd
Datapath_struc.vhd types_p.vhd
Log Message:
added "-93" to _all_ "vcom" commands in msim/compile.tcl
updated TODO
corrected DEMUX_PP to use the "MAM_i" input which determines wether the data
from RAM was MAM'ed or not. Corrected Datapath and testbench to reflect
these changes.
Moved type "Test_t" from types_p.vhd to tb_Datapath.vhd.
Index: DEMUX_PP_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/DEMUX_PP_.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** DEMUX_PP_.vhd 27 Feb 2003 10:16:02 -0000 1.3
--- DEMUX_PP_.vhd 14 May 2003 08:37:59 -0000 1.4
***************
*** 60,65 ****
Max4_o : out std_logic_vector(AnalogWidth-1 downto 0); -- output of maximum of 4th channel
MinD_o : out std_logic_vector(DigitalWidth-1 downto 0); -- output of minimum of digital channels
! MaxD_o : out std_logic_vector(DigitalWidth-1 downto 0) -- output of maximum of digital channels
! -- MAM_i : in std_logic); -- tell the Demux
! ); -- if the data from RAM has been MAM'ed or not
end DEMUX_PP;
--- 60,65 ----
Max4_o : out std_logic_vector(AnalogWidth-1 downto 0); -- output of maximum of 4th channel
MinD_o : out std_logic_vector(DigitalWidth-1 downto 0); -- output of minimum of digital channels
! MaxD_o : out std_logic_vector(DigitalWidth-1 downto 0); -- output of maximum of digital channels
! MAM_i : in std_logic -- tell the Demux
! ); -- if the data from RAM has been MAM'ed or not
end DEMUX_PP;
Index: DEMUX_PP_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/DEMUX_PP_rtl.vhd,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** DEMUX_PP_rtl.vhd 26 Feb 2003 16:37:42 -0000 1.4
--- DEMUX_PP_rtl.vhd 14 May 2003 08:38:00 -0000 1.5
***************
*** 50,95 ****
MinD_o <= RAM_i(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth);-- when MAM_I = '0' else (others => '0');
MaxD_o <= RAM_i(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth);-- when MAM_I = '0' else (others => '0');
- Avg1_o <= RAM_i( AverageWidth-1 downto 0);-- when MAM_I = '1' else (others => '0');
- Avg2_o <= RAM_i( 2*AverageWidth-1 downto AverageWidth);-- when MAM_I = '1' else (others => '0');
- Avg3_o <= RAM_i( AverageWidth-1 downto 0);-- when MAM_I = '1' else (others => '0');
- Avg4_o <= RAM_i( 2*AverageWidth-1 downto AverageWidth);-- when MAM_I = '1' else (others => '0');
-
- -- Attention: The implementation with the following process synthesizes
- -- latches for each output!!! Use the above concurrent implementation to avoid
- -- this. XSE simply uses AND gates for this. Hehe.
! -- Remark II: stupidly I thought this Demux needs to know if the incoming
! -- signals via RAM_i are either a Min/Max/Direct or a Avg1/Avg2 constellation.
! -- This is not important, because the MAM_A_P and MAM_D_P connected with it
! -- have their own ClkMin/ClkAvg1/... So they only take the signals they need.
! -- Distributing wrong signals (i.e. because of assuming a wrong input
! -- constellation) is no problem. No ClkXxx is generated.
- -- -- purpose: demultiplex data from RAM word to Min/Avg/Max of all channels
- -- -- type : combinational
- -- -- inputs : MAM_i,RAM_i
- -- -- outputs: Min[1234D]_o,Avg[1234]_o,Max[1234D]_o
- -- DEMUX: process (MAM_i,RAM_i)
- -- begin -- process DEMUX
- -- case MAM_i is
- -- when '0' => Min1_o <= RAM_i( AnalogWidth-1 downto 0);
- -- Max1_o <= RAM_i( AnalogWidth-1 downto 0);
- -- Min2_o <= RAM_i(2*AnalogWidth-1 downto AnalogWidth);
- -- Max2_o <= RAM_i(2*AnalogWidth-1 downto AnalogWidth);
- -- Min3_o <= RAM_i(3*AnalogWidth-1 downto 2*AnalogWidth);
- -- Max3_o <= RAM_i(3*AnalogWidth-1 downto 2*AnalogWidth);
- -- Min4_o <= RAM_i(4*AnalogWidth-1 downto 3*AnalogWidth);
- -- Max4_o <= RAM_i(4*AnalogWidth-1 downto 3*AnalogWidth);
- -- MinD_o <= RAM_i(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth);
- -- MaxD_o <= RAM_i(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth);
- -- when '1' => Avg1_o <= RAM_i( AverageWidth-1 downto 0);
- -- Avg2_o <= RAM_i(2*AverageWidth-1 downto AverageWidth);
- -- Avg3_o <= RAM_i( AverageWidth-1 downto 0);
- -- Avg4_o <= RAM_i(2*AverageWidth-1 downto AverageWidth);
- -- when others => null;
- -- end case;
-
- -- end process DEMUX;
-
-
end rtl;
--- 50,76 ----
MinD_o <= RAM_i(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth);-- when MAM_I = '0' else (others => '0');
MaxD_o <= RAM_i(DigitalWidth+4*AnalogWidth-1 downto 4*AnalogWidth);-- when MAM_I = '0' else (others => '0');
! -- purpose: demultiplex data from RAM word to Avg of all channels
! -- type : combinational
! -- inputs : MAM_i,RAM_i
! -- outputs: Avg[1234]_o
! DEMUX: process (MAM_i,RAM_i)
! begin -- process DEMUX
! case MAM_i is
! when '0' => Avg1_o(AnalogWidth -1 downto 0) <= RAM_i( AnalogWidth-1 downto 0);
! Avg2_o(AnalogWidth -1 downto 0) <= RAM_i(2*AnalogWidth-1 downto AnalogWidth);
! Avg3_o(AnalogWidth -1 downto 0) <= RAM_i(3*AnalogWidth-1 downto 2*AnalogWidth);
! Avg4_o(AnalogWidth -1 downto 0) <= RAM_i(4*AnalogWidth-1 downto 3*AnalogWidth);
! Avg1_o(AverageWidth-1 downto AnalogWidth) <= (others => '0');
! Avg2_o(AverageWidth-1 downto AnalogWidth) <= (others => '0');
! Avg3_o(AverageWidth-1 downto AnalogWidth) <= (others => '0');
! Avg4_o(AverageWidth-1 downto AnalogWidth) <= (others => '0');
! when others => Avg1_o <= RAM_i( AverageWidth-1 downto 0);
! Avg2_o <= RAM_i(2*AverageWidth-1 downto AverageWidth);
! Avg3_o <= RAM_i( AverageWidth-1 downto 0);
! Avg4_o <= RAM_i(2*AverageWidth-1 downto AverageWidth);
! end case;
!
! end process DEMUX;
end rtl;
Index: Datapath_.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Datapath_.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** Datapath_.vhd 9 Apr 2003 11:10:48 -0000 1.2
--- Datapath_.vhd 14 May 2003 08:38:00 -0000 1.3
***************
*** 62,65 ****
--- 62,66 ----
Through_PP_i : in std_logic; -- activate "Through_i" on MAMs at output side
En_PP_i : in std_logic; -- enable PP_Clk unit
+ MAM_PP_i : in std_logic; -- tell DEMUX_PP if data from RAM was MAM'ed or not
MAAM_PP_i : in MAAM_t; -- select which group to be routet to the µC
uC_Select_i : in std_logic_vector( 3 downto 0); -- select 8-bit packet from 72-bit data bus
Index: Datapath_struc.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Datapath_struc.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** Datapath_struc.vhd 15 Apr 2003 13:00:51 -0000 1.3
--- Datapath_struc.vhd 14 May 2003 08:38:00 -0000 1.4
***************
*** 146,152 ****
Max4_o : out std_logic_vector(AnalogWidth -1 downto 0); -- output of maximum of 4th channel
MinD_o : out std_logic_vector(DigitalWidth-1 downto 0); -- output of minimum of digital channels
! MaxD_o : out std_logic_vector(DigitalWidth-1 downto 0) -- output of maximum of digital channels
! -- MAM_i : in std_logic); -- tell the Demux
! ); -- if the data from RAM has been MAM'ed or not
end component;
--- 146,152 ----
Max4_o : out std_logic_vector(AnalogWidth -1 downto 0); -- output of maximum of 4th channel
MinD_o : out std_logic_vector(DigitalWidth-1 downto 0); -- output of minimum of digital channels
! MaxD_o : out std_logic_vector(DigitalWidth-1 downto 0); -- output of maximum of digital channels
! MAM_i : in std_logic -- tell the Demux
! ); -- if the data from RAM has been MAM'ed or not
end component;
***************
*** 459,463 ****
MinD_o => Min_D_Dig,
MaxD_o => Max_D_Dig,
! RAM_i => RAM_PP);
i_MAM_A_P_Ch1 : MAM_A_P
--- 459,464 ----
MinD_o => Min_D_Dig,
MaxD_o => Max_D_Dig,
! RAM_i => RAM_PP,
! MAM_i => MAM_PP_i);
i_MAM_A_P_Ch1 : MAM_A_P
Index: types_p.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/types_p.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** types_p.vhd 8 May 2003 14:48:39 -0000 1.3
--- types_p.vhd 14 May 2003 08:38:00 -0000 1.4
***************
*** 32,36 ****
type MAAM_t is (MAAM_Min,MAAM_Avg1,MAAM_Avg2,MAAM_Max); -- MUX selection which data group for the RAM
- type Test_t is (IdlePrep,Test1,Test2,Test3,Test4,Test5,Test6); -- for tb_Datapath
end types_p;
--- 32,35 ----
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