[Dso-cvs] FPGA/src Avg_A_rtl.vhd,1.10,1.11
Status: Planning
Brought to you by:
hansiglaser
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From: Gerald Z. <ri...@us...> - 2003-04-29 14:29:16
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Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv1125/FPGA/src
Modified Files:
Avg_A_rtl.vhd
Log Message:
Index: Avg_A_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Avg_A_rtl.vhd,v
retrieving revision 1.10
retrieving revision 1.11
diff -C2 -d -r1.10 -r1.11
*** Avg_A_rtl.vhd 29 Apr 2003 14:28:05 -0000 1.10
--- Avg_A_rtl.vhd 29 Apr 2003 14:29:11 -0000 1.11
***************
*** 46,50 ****
variable Avg_var : std_logic_vector(WidthOut-1 downto 0);
begin
! if Reset = '1' then -- asynchronous reset (active low)
Avg_var := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
--- 46,50 ----
variable Avg_var : std_logic_vector(WidthOut-1 downto 0);
begin
! if Reset = '0' then -- asynchronous reset (active low)
Avg_var := (others => '0');
elsif Clk'event and Clk = '1' then -- rising clock edge
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