[Dso-cvs] FPGA/tb tb_Datapath.vhd,1.4,1.5
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[Dso-cvs] FPGA/tb tb_Datapath.vhd,1.4,1.5
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From: Gerald Z. <ri...@us...> - 2003-04-30 11:26:35
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Update of /cvsroot/dso/FPGA/tb
In directory sc8-pr-cvs1:/tmp/cvs-serv31242/FPGA/tb
Modified Files:
tb_Datapath.vhd
Log Message:
Index: tb_Datapath.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/tb/tb_Datapath.vhd,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** tb_Datapath.vhd 29 Apr 2003 14:28:05 -0000 1.4
--- tb_Datapath.vhd 30 Apr 2003 11:26:27 -0000 1.5
***************
*** 33,36 ****
--- 33,39 ----
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed."+";
+ use IEEE.std_logic_signed.">";
+ use IEEE.std_logic_signed."<";
+ use IEEE.std_logic_unsigned.conv_integer;
use IEEE.math_real.all;
use work.all;
***************
*** 62,71 ****
signal RAMdir : std_logic := '0'; -- read/write RAM
signal EnPP : std_logic := '0'; -- enable PP_Clk
! signal ThPP : std_logic := '0'; -- enable PP-units
signal uCsel : std_logic_vector(3 downto 0) := (others => '0'); -- select 8 bit words -> output
signal RAM : std_logic_vector(RAM_Width-1 downto 0); -- RAM values
signal uC : std_logic_vector(7 downto 0); -- output to uC
! signal t_RAM : std_logic_vector(71 downto 0); -- varify RAM signal
signal cs : integer := 0; -- for testing routine
--- 65,75 ----
signal RAMdir : std_logic := '0'; -- read/write RAM
signal EnPP : std_logic := '0'; -- enable PP_Clk
! signal ThPP : std_logic := '0'; -- pass PP-units
signal uCsel : std_logic_vector(3 downto 0) := (others => '0'); -- select 8 bit words -> output
signal RAM : std_logic_vector(RAM_Width-1 downto 0); -- RAM values
signal uC : std_logic_vector(7 downto 0); -- output to uC
! signal t_RAM : std_logic_vector(71 downto 0) :=(others => 'Z'); -- varify RAM signal
! signal t_uC : std_logic_vector(7 downto 0); -- varify uC signal
signal cs : integer := 0; -- for testing routine
***************
*** 149,152 ****
--- 153,157 ----
p_input: process
variable count : integer := -50; -- count variable
+ variable incdec : integer := 1; -- increment/decrement
begin -- process p_input
I1 <= conv_std_logic_vector(5*count,AnalogWidth);
***************
*** 156,163 ****
Di <= conv_std_logic_vector(count, DigitalWidth);
! count := count + 1;
if count > 50 then
count := 50;
end if;
wait for 10 ns;
end process p_input;
--- 161,174 ----
Di <= conv_std_logic_vector(count, DigitalWidth);
! count := count + incdec;
if count > 50 then
count := 50;
+ incdec := -1;
end if;
+ if count < -50 then
+ count := -50;
+ incdec := 1;
+ end if;
+
wait for 10 ns;
end process p_input;
***************
*** 172,176 ****
begin -- process p_Test
! -- 1) test input -> RAM
-- 1.1) trough at highest rate
--- 183,187 ----
begin -- process p_Test
! -- 1) test input(4 analog channels + digital channel) -> RAM
-- 1.1) trough at highest rate
***************
*** 185,189 ****
MAAM <= MAAM_Min;
RAMdir <= '0';
! wait for 2000 ns;
-- 1.2) sampling at lower bitrate
--- 196,200 ----
MAAM <= MAAM_Min;
RAMdir <= '0';
! wait for 1000 ns;
-- 1.2) sampling at lower bitrate
***************
*** 200,204 ****
wait for 20*T2_Clk;
Latch <= '0';
! wait for 10*T2_Clk;
MAAM <= MAAM_Min;
wait for 2*T2_Clk;
--- 211,216 ----
wait for 20*T2_Clk;
Latch <= '0';
! wait for T2_Clk;
! wait on Clk;
MAAM <= MAAM_Min;
wait for 2*T2_Clk;
***************
*** 211,214 ****
--- 223,250 ----
wait for 100 ns;
+ -- 2) test RAM -> output(uC)
+ -- 2.1) stored trough signal, trough PP units
+
+ Reset <= '0';
+ wait for 20 ns;
+ Reset <= '1';
+ wait for 20 ns;
+ cs <= 3;
+ EnAD <= '0';
+ ThAD <= '0';
+ Latch <= '0';
+ EnPP <= '1';
+ ThPP <= '1';
+ MAAM <= MAAM_Max;
+ RAMdir <= '1';
+ wait for T2_Clk;
+ RAM <= "101110000110111010101111100011010101111011000011101110010101011101001011";
+ wait on Clk;
+ for i in 0 to 8 loop
+ uCsel <= conv_std_logic_vector(i,4);
+ wait for 2*T2_Clk;
+ end loop; -- i
+ RAM <= (others => 'Z');
+
***************
*** 219,227 ****
-- inputs : RAM
-- outputs:
! p_varify: process (RAM)
begin -- process p_varify
!
! assert RAM = t_RAM report "signals do not match!" severity WARNING;
!
end process p_varify;
--- 255,265 ----
-- inputs : RAM
-- outputs:
! p_varify: process (RAM,uC)
begin -- process p_varify
! if (cs <3 and cs > 0) then
! assert RAM = t_RAM report "Signals do not match, component NOT OK!" severity WARNING;
! else
! assert uC = t_uC report "Signals do not match, component NOT OK!" severity WARNING;
! end if;
end process p_varify;
***************
*** 236,243 ****
variable h_avg1,o_avg1 : std_logic_vector(71 downto 0);
variable h_avg2,o_avg2 : std_logic_vector(71 downto 0);
begin -- process p_genTest
if Reset = '0' then -- asynchronous reset (active low)
! t_RAM <= (others => '0');
! help := (others => '0');
h_min := (others => '0');
h_max := (others => '0');
--- 274,283 ----
variable h_avg1,o_avg1 : std_logic_vector(71 downto 0);
variable h_avg2,o_avg2 : std_logic_vector(71 downto 0);
+ variable llc : integer := 0; -- loop count variable
begin -- process p_genTest
if Reset = '0' then -- asynchronous reset (active low)
! t_RAM <= (others => '0');
! t_uC <= (others => '0');
! help := (others => '0');
h_min := (others => '0');
h_max := (others => '0');
***************
*** 249,252 ****
--- 289,293 ----
o_avg2 := (others => '0');
+
elsif Clk'event and Clk = '1' then -- rising clock edge
case cs is
***************
*** 257,308 ****
help( 9 downto 0) := I1;
t_RAM <= help after 2*T2_Clk;
! when 2 =>
! if I1 < h_min(9 downto 0) then
! h_min(9 downto 0) := I1;
end if;
! if I2 < h_min(19 downto 10) then
! h_min(19 downto 10) := I2;
end if;
! if I3 < h_min(29 downto 20) then
! h_min(29 downto 20) := I3;
end if;
! if I4 < h_min(39 downto 30) then
! h_min(39 downto 30) := I4;
end if;
! h_min(71 downto 40) := h_min(31 downto 0) and Di;
! if I1 > h_max(9 downto 0) then
! h_min(9 downto 0) := I1;
end if;
! if I2 > h_max(19 downto 10) then
! h_min(19 downto 10) := I2;
end if;
! if I3 > h_max(29 downto 20) then
! h_min(29 downto 20) := I3;
end if;
! if I4 > h_max(39 downto 30) then
! h_min(39 downto 30) := I4;
end if;
! h_max(71 downto 40) := h_max(31 downto 0) or Di;
! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I2;
! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I1;
! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I4;
! h_avg2(35 downto 0) := h_avg2(35 downto 0) + I3;
! if Latch='0' then
! o_min := h_min;
! o_max := h_max;
! o_avg1:= h_avg1;
! o_avg2:= h_avg2;
! end if;
! case MAAM is
! when MAAM_Min => t_RAM <= o_min;
! when MAAM_Max => t_RAM <= o_max;
! when MAAM_Avg1=> t_RAM <= o_avg1;
! when MAAM_Avg2=> t_RAM <= o_avg2;
! end case;
!
when others => null;
end case;
--- 298,353 ----
help( 9 downto 0) := I1;
t_RAM <= help after 2*T2_Clk;
! when 2 => if llc=1 then
!
! if IEEE.std_logic_signed."<"(I1'Delayed(2*T2_Clk),h_min(9 downto 0)) then
! h_min(9 downto 0) := I1'Delayed(2*T2_Clk);
end if;
! if IEEE.std_logic_signed."<"(I2'Delayed(2*T2_Clk),h_min(19 downto 10)) then
! h_min(19 downto 10) := I2'Delayed(2*T2_Clk);
end if;
! if IEEE.std_logic_signed."<"(I3'Delayed(2*T2_Clk),h_min(29 downto 20)) then
! h_min(29 downto 20) := I3'Delayed(2*T2_Clk);
end if;
! if IEEE.std_logic_signed."<"(I4'Delayed(2*T2_Clk),h_min(39 downto 30)) then
! h_min(39 downto 30) := I4'Delayed(2*T2_Clk);
end if;
! h_min(71 downto 40) := h_min(71 downto 40) and Di'Delayed(2*T2_Clk);
! if IEEE.std_logic_signed.">"(I1'Delayed(2*T2_Clk),h_max(9 downto 0)) then
! h_max(9 downto 0) := I1'Delayed(2*T2_Clk);
end if;
! if IEEE.std_logic_signed.">"(I2'Delayed(2*T2_Clk),h_max(19 downto 10)) then
! h_max(19 downto 10) := I2'Delayed(2*T2_Clk);
end if;
! if IEEE.std_logic_signed.">"(I3'Delayed(2*T2_Clk),h_max(29 downto 20)) then
! h_max(29 downto 20) := I3'Delayed(2*T2_Clk);
end if;
! if IEEE.std_logic_signed.">"(I4'Delayed(2*T2_Clk),h_max(39 downto 30)) then
! h_max(39 downto 30) := I4'Delayed(2*T2_Clk);
end if;
! h_max(71 downto 40) := h_max(71 downto 40) or Di'Delayed(2*T2_Clk);
! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I2'Delayed(2*T2_Clk);
! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I1'Delayed(2*T2_Clk);
! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I4'Delayed(2*T2_Clk);
! h_avg2(35 downto 0) := h_avg2(35 downto 0) + I3'Delayed(2*T2_Clk);
! if Latch='1' then
! o_min := h_min;
! o_max := h_max;
! o_avg1:= h_avg1;
! o_avg2:= h_avg2;
! end if;
! case MAAM is
! when MAAM_Min => t_RAM <= o_min ;
! when MAAM_Max => t_RAM <= o_max ;
! when MAAM_Avg1=> t_RAM <= o_avg1;
! when MAAM_Avg2=> t_RAM <= o_avg2;
! end case;
! else
! llc:=1; -- one period delay
! end if;
! when 3 => t_uC <= RAM((conv_integer(uCsel)+1)*8-1 downto conv_integer(uCsel)*8);
when others => null;
end case;
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