[Dso-cvs] FPGA/dc command.log,1.2,1.3 view_command.log,1.1,1.2

[Johann G. <han...@us...>]

Update of /cvsroot/dso/FPGA/dc
In directory sc8-pr-cvs1:/tmp/cvs-serv21152

Modified Files:
	command.log view_command.log 
Log Message:



Index: command.log
===================================================================
RCS file: /cvsroot/dso/FPGA/dc/command.log,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** command.log	15 May 2003 08:00:27 -0000	1.2
--- command.log	15 May 2003 08:15:44 -0000	1.3
***************
*** 1,4 ****
! /* krypton -- Thu May 15 09:56:17 2003
!    Initial dc_shell Variable Values */
  
  
--- 1,4 ----
! /* krypton -- Thu May 15 10:05:49 2003
!    Initial design_analyzer Variable Values */
  
  
***************
*** 6,32 ****
  _bs_suppress_errors = {"PWR-18", "OPT-931", "OPT-932"}
  _bs_valid_program = "true"
- acs_area_report_suffix = "area"
- acs_bs_exec = ""
- acs_budget_output_file_suffix = "btcl.out"
- acs_budget_script_file_suffix = "btcl"
- acs_budgeted_cstr_suffix = "con"
- acs_compile_script_suffix = "autoscr"
- acs_constraint_file_suffix = "con"
- acs_cstr_report_suffix = "cstr"
- acs_db_suffix = "db"
- acs_dc_exec = ""
- acs_global_user_compile_strategy_script = "default.compile"
- acs_log_file_suffix = "log"
- acs_makefile_name = "Makefile"
- acs_num_parallel_jobs = "1"
- acs_override_script_suffix = "scr"
- acs_qor_report_suffix = "qor"
- acs_script_mode = "dcsh"
- acs_timing_report_suffix = "tim"
- acs_tr_exec = ""
- acs_use_lsf = "false"
- acs_user_budgeting_script = "budget.scr"
- acs_user_compile_strategy_script_suffix = "compile"
- acs_work_dir = "/a/ursus/chip004/hansi/FPGA/dc"
  atpg_bidirect_output_only = "false"
  atpg_test_asynchronous_pins = "true"
--- 6,9 ----
***************
*** 71,75 ****
  change_names_dont_change_bus_members = "false"
  change_names_update_inst_tree = "true"
- check_error_list = {"CMD-004", "CMD-006", "CMD-007", "CMD-008", "CMD-009", "CMD-010", "CMD-011", "CMD-012", "CMD-014", "CMD-015", "CMD-016", "CMD-019", "CMD-026", "CMD-031", "CMD-037", "DB-1", "DCSH-11", "DES-001", "FILE-1", "FILE-2", "FILE-3", "FILE-4", "LINK-5", "LINK-7", "LINT-7", "LINT-20", "LNK-023", "OPT-100", "OPT-101", "OPT-102", "OPT-114", "OPT-124", "OPT-127", "OPT-128", "OPT-155", "OPT-157", "OPT-181", "OPT-462", "UI-11", "UI-14", "UI-15", "UI-16", "UI-17", "UI-19", "UI-20", "UI-21", "UI-22", "UI-23", "UI-40", "UI-41", "UID-4", "UID-6", "UID-7", "UID-8", "UID-9", "UID-13", "UID-14", "UID-15", "UID-19", "UID-20", "UID-25", "UID-27", "UID-28", "UID-29", "UID-30", "UID-32", "UID-58", "UID-87", "UID-103", "UID-109", "UID-270", "UID-272", "UID-403", "UID-440", "UID-444", "UIO-2", "UIO-3", "UIO-4", "UIO-25", "UIO-65", "UIO-66", "UIO-75", "UIO-94", "UIO-95", "EQN-6", "EQN-11", "EQN-15", "EQN-16", "EQN-18", "EQN-20"}
  command_log_file = "./command.log"
  company = "Vienna University of Technology"
--- 48,51 ----
***************
*** 132,138 ****
  dc_shell_mode = "default"
  dc_shell_status = 1
- default_input_delay = 30.000000
  default_name_rules = ""
- default_output_delay = 30.000000
  default_port_connection_class = "universal"
  default_schematic_options = "-size infinite"
--- 108,112 ----
***************
*** 399,402 ****
--- 373,377 ----
  sh_enable_page_mode = "true"
  sh_source_uses_search_path = "true"
+ shell_prompt = "design_analyzer> "
  single_group_per_sheet = "false"
  site_info_file = "/home/synopsys/9910/admin/license/site_info"
***************
*** 539,542 ****
--- 514,518 ----
  view_background = "black"
  view_cache_images = "true"
+ view_clear_whole_area_on_delete = "false"
  view_command_log_file = "./view_command.log"
  view_command_win_max_lines = 1000
***************
*** 547,555 ****
--- 523,537 ----
  view_error_window_count = 6
  view_execute_script_suffix = {".script", ".scr", ".dcs", ".dcv", ".dc", ".con"}
+ view_image_cache_options = 1
  view_info_search_cmd = "/home/synopsys/9910/infosearch/scripts/InfoSearch"
+ view_linear_box_search_percentage = 95
+ view_linear_line_search_percentage = 85
  view_log_file = ""
+ view_max_image_size_to_cache = 175
  view_on_line_doc_cmd = "/home/synopsys/9910/sold"
  view_read_file_suffix = {"db", "gdb", "sdb", "edif", "eqn", "fnc", "lsi", "mif", "NET", "pla", "st", "tdl", "v", "vhd", "vhdl", "xnf"}
  view_script_submenu_items = {"DA to SGE Transfer", "write_sge"}
+ view_set_draw_interrupt_limit = 500
+ view_set_select_interrupt_limit = 200
  view_tools_menu_items = {}
  view_use_small_cursor = ""
***************
*** 567,573 ****
--- 549,560 ----
  write_test_scan_check_file_naming_style = "%s_schk.%s"
  write_test_vector_file_naming_style = "%s_%d.%s"
+ x11_display_string = "krypton:12.0"
+ x11_is_color = "true"
  x11_set_cursor_background = ""
  x11_set_cursor_foreground = ""
  x11_set_cursor_number = -1
+ x11_vendor_release_number = 7000
+ x11_vendor_string = "Humming"
+ x11_vendor_version_number = 11
  xnfin_dff_clock_enable_pin_name = "CE"
  xnfin_dff_clock_pin_name = "C"
***************
*** 585,589 ****
  
  
! /* Initial dc_shell Aliases */
  
  
--- 572,576 ----
  
  
! /* Initial design_analyzer Aliases */
  
  
***************
*** 630,700 ****
  
  
! /* dc_shell Command Log */ 
  
  
! /* ----------------------------------------------------- */ 
! /* This is the synthesis script for the fulladder design */ 
! /* ----------------------------------------------------- */ 
! /* write some informative data to the log file */ 
! sh date 
! sh hostname 
! /* main module of our design */ 
! main_module = datapath 
! /* file list of our design, without ".vhd" extension */ 
! file_list = {Avg_A_, \
! Avg_A_rtl, \
! DEMUX_PP_, \
! DEMUX_PP_rtl, \
! Datapath_, \
! Datapath_struc, \
! Join_Avg_, \
! Join_Avg_struc, \
! Join_MinMax_, \
! Join_MinMax_struc, \
! Latch_A_, \
! Latch_A_rtl, \
! Latch_D_, \
! Latch_D_rtl, \
! MAM_A_, \
! MAM_A_P_, \
! MAM_A_P_struc, \
! MAM_A_struc, \
! MAM_D_, \
! MAM_D_P_, \
! MAM_D_P_struc, \
! MAM_D_struc, \
! MUX_4_N_, \
! MUX_4_N_rtl, \
! MUX_AD_, \
! MUX_AD_struc, \
! MUX_N_1_, \
! MUX_N_1_rtl, \
! MUX_RAM_, \
! MUX_RAM_rtl, \
! MUX_uC_, \
! MUX_uC_rtl, \
! Max_A_, \
! Max_A_rtl, \
! Max_D_, \
! Max_D_rtl, \
! Min_A_, \
! Min_A_rtl, \
! Min_D_, \
! Min_D_rtl, \
! PP_Clk_, \
! PP_Clk_rtl, \
! types_p } 
! /* directory structure variables used later in the script */ 
! db_area = "./db/" 
! vhd_area = "../src/" 
! report_area = "./reports/" 
! script_area = "./scr/" 
! /* analyze every VHDL file only for syntax */ 
! foreach (member, file_list) { 
!    analyze -format vhdl vhd_area + member + ".vhd" 
!    if (dc_shell_status == 0) { 
!       echo "ANALYSIS ERROR OR FILE " member " NOT FOUND" 
!       quit 
!    } 
! } 
! elaborate main_module -update 
--- 617,639 ----
  
  
! /* design_analyzer Command Log */ 
  
  
! read -format db {"/a/ursus/chip004/hansi/FPGA/dc/db/datapath_pre.db"} 
! create_schematic -size infinite    -gen_database  
! create_schematic -size infinite  -symbol_view    
! create_schematic -size infinite   -hier_view   
! create_schematic -size infinite -schematic_view     
! current_instance "i_MUX_RAM" 
! create_schematic -size infinite  -symbol_view   -reference 
! create_schematic -size infinite   -hier_view  -reference 
! create_schematic -size infinite -schematic_view    -reference 
! current_instance ".." 
! current_instance "i_MAM_D_Dig" 
! create_schematic -size infinite  -symbol_view   -reference 
! create_schematic -size infinite   -hier_view  -reference 
! create_schematic -size infinite -schematic_view    -reference 
! current_instance ".." 
! current_instance "i_MAM_A_Ch1" 
! create_schematic -size infinite  -symbol_view   -reference 
! create_schematic -size infinite   -hier_view  -reference 

Index: view_command.log
===================================================================
RCS file: /cvsroot/dso/FPGA/dc/view_command.log,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** view_command.log	15 May 2003 07:57:34 -0000	1.1
--- view_command.log	15 May 2003 08:15:44 -0000	1.2
***************
*** 17,24 ****
                Copyright (c) 1988-1999 by Synopsys, Inc.
                           ALL RIGHTS RESERVED
! design_analyzer> read -format db {"/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db"}
! Loading db file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db'
! Current design is now '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder'
! {"fulladder", "or_gate", "halfadder"}
  design_analyzer> create_schematic -size infinite    -gen_database 
  Loading db file '/home/synopsys/9910/libraries/syn/generic.sdb'
--- 17,24 ----
                Copyright (c) 1988-1999 by Synopsys, Inc.
                           ALL RIGHTS RESERVED
! design_analyzer> read -format db {"/a/ursus/chip004/hansi/FPGA/dc/db/datapath_pre.db"}
! Loading db file '/a/ursus/chip004/hansi/FPGA/dc/db/datapath_pre.db'
! Current design is now '/a/ursus/chip004/hansi/FPGA/dc/db/datapath_pre.db:Datapath'
! {"Datapath", "MAM_D_P_DigitalWidth32", "MAM_A_P_AnalogWidth10_AverageWidth36", "MUX_RAM_RAM_Width72", "MUX_AD_AnalogWidth10_AverageWidth36_DigitalWidth32_RAM_Width72", "Join_Avg_AverageWidth36_RAM_Width72", "Join_MinMax_AnalogWidth10_DigitalWidth32_RAM_Width72", "MAM_D_DigitalWidth32", "MAM_A_AnalogWidth10_AverageWidth36", "MUX_uC", "PP_Clk"}
  design_analyzer> create_schematic -size infinite    -gen_database 
  Loading db file '/home/synopsys/9910/libraries/syn/generic.sdb'
***************
*** 30,45 ****
  Loading db file '/home/synopsys/9910/libraries/syn/gtech.db'
  Loading db file '/home/synopsys/9910/libraries/syn/standard.sldb'
  create_schematic -size infinite  -symbol_view   
  1
  design_analyzer> create_schematic -size infinite   -hier_view  
  1
  design_analyzer> create_schematic -size infinite -schematic_view    
! Generating schematic for design: fulladder
! The schematic for design 'fulladder' has 1 page(s).
  
  1
! design_analyzer> current_instance "i_halfadder2"
! Current instance is '/fulladder/i_halfadder2'.
! "/fulladder/i_halfadder2"
  design_analyzer> create_schematic -size infinite  -symbol_view   -reference
  1
--- 30,154 ----
  Loading db file '/home/synopsys/9910/libraries/syn/gtech.db'
  Loading db file '/home/synopsys/9910/libraries/syn/standard.sldb'
+ Information: Building the design 'Latch_A' instantiated from design 'Datapath' with
+ 	the parameters "AnalogWidth => 10, AverageWidth => 36". (HDL-193)
+ Reading in the Synopsys vhdl primitives.
+ Error: Tried to use a synchronized value 
+ 	in call to '<='
+ 	called from Latch_A_AnalogWidth10_AverageWidth36 line 59 in file '/a/ursus/chip004/hansi/FPGA/src/Latch_A_rtl.vhd' (HDL-107)
+ Error: 'Latch_A' was not identified as a synthetic library module
+ 	and could not be successfully elaborated from design library 'work'. (LINK-10)
+ Warning: Unable to resolve reference 'Latch_A_AnalogWidth10_AverageWidth36' in 'Datapath'. (LINK-5)
+ Information: Building the design 'Latch_D' instantiated from design 'Datapath' with
+ 	the parameters "DigitalWidth => 32". (HDL-193)
+ Error: Tried to use a synchronized value 
+ 	in call to '<='
+ 	called from Latch_D_DigitalWidth32 line 53 in file '/a/ursus/chip004/hansi/FPGA/src/Latch_D_rtl.vhd' (HDL-107)
+ Error: 'Latch_D' was not identified as a synthetic library module
+ 	and could not be successfully elaborated from design library 'work'. (LINK-10)
+ Warning: Unable to resolve reference 'Latch_D_DigitalWidth32' in 'Datapath'. (LINK-5)
+ Information: Building the design 'DEMUX_PP' instantiated from design 'Datapath' with
+ 	the parameters "AnalogWidth => 10, AverageWidth => 36, DigitalWidth => 32, RAM_Width => 72". (HDL-193)
+ Error: Can't determine type of aggregate or concat 
+ 	in routine DEMUX_PP_AnalogWidth10_AverageWidth36_DigitalWidth32_RAM_Width72 line 64 in file '/a/ursus/chip004/hansi/FPGA/src/DEMUX_PP_rtl.vhd' (HDL-123)
+ Error: 'DEMUX_PP' was not identified as a synthetic library module
+ 	and could not be successfully elaborated from design library 'work'. (LINK-10)
+ Warning: Unable to resolve reference 'DEMUX_PP_AnalogWidth10_AverageWidth36_DigitalWidth32_RAM_Width72' in 'Datapath'. (LINK-5)
+ Information: Building the design 'Min_A' instantiated from design 'MAM_A_AnalogWidth10_AverageWidth36' with
+ 	the parameters "Width => 10". (HDL-193)
+ Error: Tried to use a synchronized value 
+ 	in call to '<='
+ 	called from Min_A_Width10 line 55 in file '/a/ursus/chip004/hansi/FPGA/src/Min_A_rtl.vhd' (HDL-107)
+ Error: Additional errors suppressed.
+ 	See the Command Window for a full error message listing. (MOUI-21)
+ Error: 'Min_A' was not identified as a synthetic library module
+ 	and could not be successfully elaborated from design library 'WORK'. (LINK-10)
+ Warning: Unable to resolve reference 'Min_A_Width10' in 'datapath_pre.db:MAM_A_AnalogWidth10_AverageWidth36'. (LINK-5)
+ Information: Building the design 'Avg_A' instantiated from design 'MAM_A_AnalogWidth10_AverageWidth36' with
+ 	the parameters "WidthIn => 10, WidthOut => 36". (HDL-193)
+ Error: Can't determine type of aggregate or concat 
+ 	in routine Avg_A_WidthIn10_WidthOut36 line 57 in file '/a/ursus/chip004/hansi/FPGA/src/Avg_A_rtl.vhd' (HDL-123)
+ Error: 'Avg_A' was not identified as a synthetic library module
+ 	and could not be successfully elaborated from design library 'WORK'. (LINK-10)
+ Warning: Unable to resolve reference 'Avg_A_WidthIn10_WidthOut36' in 'datapath_pre.db:MAM_A_AnalogWidth10_AverageWidth36'. (LINK-5)
+ Information: Building the design 'Max_A' instantiated from design 'MAM_A_AnalogWidth10_AverageWidth36' with
+ 	the parameters "Width => 10". (HDL-193)
+ Error: Tried to use a synchronized value 
+ 	in call to '<='
+ 	called from Max_A_Width10 line 55 in file '/a/ursus/chip004/hansi/FPGA/src/Max_A_rtl.vhd' (HDL-107)
+ Error: 'Max_A' was not identified as a synthetic library module
+ 	and could not be successfully elaborated from design library 'WORK'. (LINK-10)
+ Warning: Unable to resolve reference 'Max_A_Width10' in 'datapath_pre.db:MAM_A_AnalogWidth10_AverageWidth36'. (LINK-5)
+ Information: Building the design 'Min_D' instantiated from design 'MAM_D_DigitalWidth32' with
+ 	the parameters "Width => 32". (HDL-193)
+ Error: Tried to use a synchronized value 
+ 	in call to '<='
+ 	called from Min_D_Width32 line 58 in file '/a/ursus/chip004/hansi/FPGA/src/Min_D_rtl.vhd' (HDL-107)
+ Error: 'Min_D' was not identified as a synthetic library module
+ 	and could not be successfully elaborated from design library 'WORK'. (LINK-10)
+ Warning: Unable to resolve reference 'Min_D_Width32' in 'datapath_pre.db:MAM_D_DigitalWidth32'. (LINK-5)
+ Information: Building the design 'Max_D' instantiated from design 'MAM_D_DigitalWidth32' with
+ 	the parameters "Width => 32". (HDL-193)
+ Error: Tried to use a synchronized value 
+ 	in call to '<='
+ 	called from Max_D_Width32 line 58 in file '/a/ursus/chip004/hansi/FPGA/src/Max_D_rtl.vhd' (HDL-107)
+ Error: 'Max_D' was not identified as a synthetic library module
+ 	and could not be successfully elaborated from design library 'WORK'. (LINK-10)
+ Warning: Unable to resolve reference 'Max_D_Width32' in 'datapath_pre.db:MAM_D_DigitalWidth32'. (LINK-5)
+ Information: Building the design 'Min_A' instantiated from design 'MAM_A_P_AnalogWidth10_AverageWidth36' with
+ 	the parameters "Width => 10". (HDL-193)
+ Error: Tried to use a synchronized value 
+ 	in call to '<='
+ 	called from Min_A_Width10 line 55 in file '/a/ursus/chip004/hansi/FPGA/src/Min_A_rtl.vhd' (HDL-107)
+ Error: 'Min_A' was not identified as a synthetic library module
+ 	and could not be successfully elaborated from design library 'WORK'. (LINK-10)
+ Warning: Unable to resolve reference 'Min_A_Width10' in 'datapath_pre.db:MAM_A_P_AnalogWidth10_AverageWidth36'. (LINK-5)
+ Information: Building the design 'Avg_A' instantiated from design 'MAM_A_P_AnalogWidth10_AverageWidth36' with
+ 	the parameters "WidthIn => 36, WidthOut => 36". (HDL-193)
+ Error: Tried to use a synchronized value 
+ 	in call to '<='
+ 	called from Avg_A_WidthIn36_WidthOut36 line 64 in file '/a/ursus/chip004/hansi/FPGA/src/Avg_A_rtl.vhd' (HDL-107)
+ Error: 'Avg_A' was not identified as a synthetic library module
+ 	and could not be successfully elaborated from design library 'WORK'. (LINK-10)
+ Warning: Unable to resolve reference 'Avg_A_WidthIn36_WidthOut36' in 'datapath_pre.db:MAM_A_P_AnalogWidth10_AverageWidth36'. (LINK-5)
+ Information: Building the design 'Max_A' instantiated from design 'MAM_A_P_AnalogWidth10_AverageWidth36' with
+ 	the parameters "Width => 10". (HDL-193)
+ Error: Tried to use a synchronized value 
+ 	in call to '<='
+ 	called from Max_A_Width10 line 55 in file '/a/ursus/chip004/hansi/FPGA/src/Max_A_rtl.vhd' (HDL-107)
+ Error: 'Max_A' was not identified as a synthetic library module
+ 	and could not be successfully elaborated from design library 'WORK'. (LINK-10)
+ Warning: Unable to resolve reference 'Max_A_Width10' in 'datapath_pre.db:MAM_A_P_AnalogWidth10_AverageWidth36'. (LINK-5)
+ Information: Building the design 'Min_D' instantiated from design 'MAM_D_P_DigitalWidth32' with
+ 	the parameters "Width => 32". (HDL-193)
+ Error: Tried to use a synchronized value 
+ 	in call to '<='
+ 	called from Min_D_Width32 line 58 in file '/a/ursus/chip004/hansi/FPGA/src/Min_D_rtl.vhd' (HDL-107)
+ Error: 'Min_D' was not identified as a synthetic library module
+ 	and could not be successfully elaborated from design library 'work'. (LINK-10)
+ Warning: Unable to resolve reference 'Min_D_Width32' in 'datapath_pre.db:MAM_D_P_DigitalWidth32'. (LINK-5)
+ Information: Building the design 'Max_D' instantiated from design 'MAM_D_P_DigitalWidth32' with
+ 	the parameters "Width => 32". (HDL-193)
+ Error: Tried to use a synchronized value 
+ 	in call to '<='
+ 	called from Max_D_Width32 line 58 in file '/a/ursus/chip004/hansi/FPGA/src/Max_D_rtl.vhd' (HDL-107)
+ Error: 'Max_D' was not identified as a synthetic library module
+ 	and could not be successfully elaborated from design library 'work'. (LINK-10)
+ Warning: Unable to resolve reference 'Max_D_Width32' in 'datapath_pre.db:MAM_D_P_DigitalWidth32'. (LINK-5)
  create_schematic -size infinite  -symbol_view   
+ Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341)
  1
  design_analyzer> create_schematic -size infinite   -hier_view  
+ Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341)
  1
  design_analyzer> create_schematic -size infinite -schematic_view    
! Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341)
! Generating schematic for design: Datapath
! The schematic for design 'Datapath' has 1 page(s).
  
  1
! design_analyzer> current_instance "i_MUX_RAM"
! Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341)
! Current instance is '/Datapath/i_MUX_RAM'.
! "/Datapath/i_MUX_RAM"
  design_analyzer> create_schematic -size infinite  -symbol_view   -reference
  1
***************
*** 47,127 ****
  1
  design_analyzer> create_schematic -size infinite -schematic_view    -reference
! Generating schematic for design: halfadder
! The schematic for design 'halfadder' has 1 page(s).
  
  1
- design_analyzer> read -format db {"/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db"}
- Loading db file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db'
- Current design is now '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder'
- {"fulladder"}
- design_analyzer> create_schematic -size infinite    -gen_database 
- 1
- design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder"
- Current design is 'fulladder'.
- {"fulladder"}
- design_analyzer> current_instance "i_halfadder2"
- Current instance is '/fulladder/i_halfadder2'.
- "/fulladder/i_halfadder2"
- design_analyzer> read -format db {"/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db"}
- Loading db file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db'
- Warning: Overwriting design file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db'. (DDB-24)
- Current design is now '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder'
- {"fulladder"}
- design_analyzer> create_schematic -size infinite    -gen_database 
- 1
- design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder"
- Current design is 'fulladder'.
- {"fulladder"}
- design_analyzer> current_instance "i_halfadder2"
- Current instance is '/fulladder/i_halfadder2'.
- "/fulladder/i_halfadder2"
  design_analyzer> current_instance ".."
! Current instance is the top-level of design 'fulladder'.
  ""
! design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder"
! Current design is 'fulladder'.
! {"fulladder"}
! design_analyzer> reset_design
! Resetting current design 'fulladder'
! 1
! design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder"
! Current design is 'fulladder'.
! {"fulladder"}
! design_analyzer> reset_design
! Resetting current design 'fulladder'
! 1
! design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:halfadder"
! Current design is 'halfadder'.
! {"halfadder"}
! design_analyzer> reset_design
! Resetting current design 'halfadder'
! 1
! design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:or_gate"
! Current design is 'or_gate'.
! {"or_gate"}
! design_analyzer> reset_design
! Resetting current design 'or_gate'
  1
! design_analyzer> read -format db {"/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db"}
! Loading db file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db'
! Warning: Overwriting design file '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db'. (DDB-24)
! Current design is now '/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder'
! {"fulladder"}
! design_analyzer> create_schematic -size infinite    -gen_database 
  1
! design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder_pre.db:fulladder"
! Current design is 'fulladder'.
! {"fulladder"}
! design_analyzer> current_design "/a/ursus/chip004/vhdl_demoexpls/fulladder/dc/db/fulladder.db:fulladder"
! Current design is 'fulladder'.
! {"fulladder"}
! design_analyzer> create_schematic -size infinite  -symbol_view   
  1
! design_analyzer> create_schematic -size infinite   -hier_view  
  1
! design_analyzer> create_schematic -size infinite -schematic_view    
! Generating schematic for design: fulladder
! The schematic for design 'fulladder' has 1 page(s).
! 
  1
! design_analyzer> 
\ No newline at end of file
--- 156,236 ----
  1
  design_analyzer> create_schematic -size infinite -schematic_view    -reference
! Generating schematic for design: MUX_RAM_RAM_Width72
! The schematic for design 'MUX_RAM_RAM_Width72' has 1 page(s).
  
  1
  design_analyzer> current_instance ".."
! Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341)
! Current instance is the top-level of design 'Datapath'.
  ""
! design_analyzer> Information: Building the design 'Min_D' instantiated from design 'MAM_D_DigitalWidth32' with
! 	the parameters "Width => 32". (HDL-193)
! Error: Tried to use a synchronized value 
! 	in call to '<='
! 	called from Min_D_Width32 line 58 in file '/a/ursus/chip004/hansi/FPGA/src/Min_D_rtl.vhd' (HDL-107)
! Error: 'Min_D' was not identified as a synthetic library module
! 	and could not be successfully elaborated from design library 'WORK'. (LINK-10)
! Warning: Unable to resolve reference 'Min_D_Width32' in 'MAM_D_DigitalWidth32'. (LINK-5)
! Information: Building the design 'Max_D' instantiated from design 'MAM_D_DigitalWidth32' with
! 	the parameters "Width => 32". (HDL-193)
! Error: Tried to use a synchronized value 
! 	in call to '<='
! 	called from Max_D_Width32 line 58 in file '/a/ursus/chip004/hansi/FPGA/src/Max_D_rtl.vhd' (HDL-107)
! Error: 'Max_D' was not identified as a synthetic library module
! 	and could not be successfully elaborated from design library 'WORK'. (LINK-10)
! Warning: Unable to resolve reference 'Max_D_Width32' in 'MAM_D_DigitalWidth32'. (LINK-5)
! current_instance "i_MAM_D_Dig"
! Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341)
! Current instance is '/Datapath/i_MAM_D_Dig'.
! "/Datapath/i_MAM_D_Dig"
! design_analyzer> create_schematic -size infinite  -symbol_view   -reference
! Warning: Design 'MAM_D_DigitalWidth32' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341)
  1
! design_analyzer> create_schematic -size infinite   -hier_view  -reference
! Warning: Design 'MAM_D_DigitalWidth32' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341)
  1
! design_analyzer> create_schematic -size infinite -schematic_view    -reference
! Warning: Design 'MAM_D_DigitalWidth32' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341)
! Generating schematic for design: MAM_D_DigitalWidth32
! The schematic for design 'MAM_D_DigitalWidth32' has 1 page(s).
! 
  1
! design_analyzer> current_instance ".."
! Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341)
! Current instance is the top-level of design 'Datapath'.
! ""
! design_analyzer> Information: Building the design 'Min_A' instantiated from design 'MAM_A_AnalogWidth10_AverageWidth36' with
! 	the parameters "Width => 10". (HDL-193)
! Error: Tried to use a synchronized value 
! 	in call to '<='
! 	called from Min_A_Width10 line 55 in file '/a/ursus/chip004/hansi/FPGA/src/Min_A_rtl.vhd' (HDL-107)
! Error: 'Min_A' was not identified as a synthetic library module
! 	and could not be successfully elaborated from design library 'WORK'. (LINK-10)
! Warning: Unable to resolve reference 'Min_A_Width10' in 'MAM_A_AnalogWidth10_AverageWidth36'. (LINK-5)
! Information: Building the design 'Avg_A' instantiated from design 'MAM_A_AnalogWidth10_AverageWidth36' with
! 	the parameters "WidthIn => 10, WidthOut => 36". (HDL-193)
! Error: Can't determine type of aggregate or concat 
! 	in routine Avg_A_WidthIn10_WidthOut36 line 57 in file '/a/ursus/chip004/hansi/FPGA/src/Avg_A_rtl.vhd' (HDL-123)
! Error: 'Avg_A' was not identified as a synthetic library module
! 	and could not be successfully elaborated from design library 'WORK'. (LINK-10)
! Warning: Unable to resolve reference 'Avg_A_WidthIn10_WidthOut36' in 'MAM_A_AnalogWidth10_AverageWidth36'. (LINK-5)
! Information: Building the design 'Max_A' instantiated from design 'MAM_A_AnalogWidth10_AverageWidth36' with
! 	the parameters "Width => 10". (HDL-193)
! Error: Tried to use a synchronized value 
! 	in call to '<='
! 	called from Max_A_Width10 line 55 in file '/a/ursus/chip004/hansi/FPGA/src/Max_A_rtl.vhd' (HDL-107)
! Error: 'Max_A' was not identified as a synthetic library module
! 	and could not be successfully elaborated from design library 'WORK'. (LINK-10)
! Warning: Unable to resolve reference 'Max_A_Width10' in 'MAM_A_AnalogWidth10_AverageWidth36'. (LINK-5)
! current_instance "i_MAM_A_Ch1"
! Warning: Design 'Datapath' has '13' unresolved references. For more detailed information, use the "link" command. (UID-341)
! Current instance is '/Datapath/i_MAM_A_Ch1'.
! "/Datapath/i_MAM_A_Ch1"
! design_analyzer> create_schematic -size infinite  -symbol_view   -reference
! Warning: Design 'MAM_A_AnalogWidth10_AverageWidth36' has '3' unresolved references. For more detailed information, use the "link" command. (UID-341)
  1
! design_analyzer> create_schematic -size infinite   -hier_view  -reference
! Warning: Design 'MAM_A_AnalogWidth10_AverageWidth36' has '3' unresolved references. For more detailed information, use the "link" command. (UID-341)
  1
! design_analyzer> 
! Thank you...