[Dso-cvs] FPGA/src Avg_A_rtl.vhd,1.9,1.10

[Gerald Z. <ri...@us...>]

Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv456/FPGA/src

Modified Files:
	Avg_A_rtl.vhd 
Log Message:



Index: Avg_A_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Avg_A_rtl.vhd,v
retrieving revision 1.9
retrieving revision 1.10
diff -C2 -d -r1.9 -r1.10
*** Avg_A_rtl.vhd	8 Apr 2003 13:25:15 -0000	1.9
--- Avg_A_rtl.vhd	29 Apr 2003 14:28:05 -0000	1.10
***************
*** 46,50 ****
      variable Avg_var : std_logic_vector(WidthOut-1 downto 0);
    begin
!     if Reset = '0' then                 -- asynchronous reset (active low)
        Avg_var := (others => '0');
      elsif Clk'event and Clk = '1' then  -- rising clock edge
--- 46,50 ----
      variable Avg_var : std_logic_vector(WidthOut-1 downto 0);
    begin
!     if Reset = '1' then                 -- asynchronous reset (active low)
        Avg_var := (others => '0');
      elsif Clk'event and Clk = '1' then  -- rising clock edge