[Dso-cvs] FPGA TODO,1.6,1.7

[Johann G. <han...@us...>]

Update of /cvsroot/dso/FPGA
In directory sc8-pr-cvs1:/tmp/cvs-serv26131

Modified Files:
	TODO 
Log Message:
added "-93" to _all_ "vcom" commands in msim/compile.tcl
updated TODO
corrected DEMUX_PP to use the "MAM_i" input which determines wether the data
  from RAM was MAM'ed or not. Corrected Datapath and testbench to reflect
  these changes.
Moved type "Test_t" from types_p.vhd to tb_Datapath.vhd.


Index: TODO
===================================================================
RCS file: /cvsroot/dso/FPGA/TODO,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** TODO	9 Apr 2003 11:43:54 -0000	1.6
--- TODO	14 May 2003 08:37:57 -0000	1.7
***************
*** 1,5 ****
  
  - Architectures for DSO, Control, Kernel and Trigger
! - Testbench for Datapath
  - tb_MAM_A.vhd: line 84: "1=1" -- can be written as "(true)"
  - tb_Avg_A.vhd: clock and reset are modelled awkwardly
--- 1,7 ----
  
  - Architectures for DSO, Control, Kernel and Trigger
! - Datapath: DEMUX_PP must have an input to select which signals to put to
!   the Avg outputs, either if they come from a stored "Avg1:Avg2"/"Avg3:Avg4"
!   or they come from a stored "Val1:Val2:Val3:Val4:Dig"
  - tb_MAM_A.vhd: line 84: "1=1" -- can be written as "(true)"
  - tb_Avg_A.vhd: clock and reset are modelled awkwardly