[Dso-cvs] FPGA/dc/scr synth_dc.scr,NONE,1.1

[Johann G. <han...@us...>]

Update of /cvsroot/dso/FPGA/dc/scr
In directory sc8-pr-cvs1:/tmp/cvs-serv15764/scr

Added Files:
	synth_dc.scr 
Log Message:



--- NEW FILE: synth_dc.scr ---
/* ----------------------------------------------------- */
/* This is the synthesis script for the fulladder design */
/* ----------------------------------------------------- */

/* write some informative data to the log file */
sh date
sh hostname

/* main module of our design */
main_module = datapath

/* file list of our design, without ".vhd" extension */
file_list = {Avg_A_, \
Avg_A_rtl, \
DEMUX_PP_, \
DEMUX_PP_rtl, \
Datapath_, \
Datapath_struc, \
Join_Avg_, \
Join_Avg_struc, \
Join_MinMax_, \
Join_MinMax_struc, \
Latch_A_, \
Latch_A_rtl, \
Latch_D_, \
Latch_D_rtl, \
MAM_A_, \
MAM_A_P_, \
MAM_A_P_struc, \
MAM_A_struc, \
MAM_D_, \
MAM_D_P_, \
MAM_D_P_struc, \
MAM_D_struc, \
MUX_4_N_, \
MUX_4_N_rtl, \
MUX_AD_, \
MUX_AD_struc, \
MUX_N_1_, \
MUX_N_1_rtl, \
MUX_RAM_, \
MUX_RAM_rtl, \
MUX_uC_, \
MUX_uC_rtl, \
Max_A_, \
Max_A_rtl, \
Max_D_, \
Max_D_rtl, \
Min_A_, \
Min_A_rtl, \
Min_D_, \
Min_D_rtl, \
PP_Clk_, \
PP_Clk_rtl, \
types_p }

/* directory structure variables used later in the script */
db_area = "./db/"
vhd_area = "../src/"
report_area = "./reports/"
script_area = "./scr/"

/* analyze every VHDL file only for syntax */
foreach (member, file_list) {
   analyze -format vhdl vhd_area + member + ".vhd"
   if (dc_shell_status == 0) {
      echo "ANALYSIS ERROR OR FILE " member " NOT FOUND"
      quit
   }
}

elaborate main_module -update

check_design

write -f db -h -o db_area + main_module + "_pre.db"

/* every net gets its unique name */
uniquify

/* remove hierarchy from design */
ungroup -all -flatten

/* set main module for following commands */
current_design = main_module

/* setup design parameters */
set_wire_load "0to50" -library MTC45000_WL_WORST
set_operating_conditions WCCOM
set_driving_cell -cell IV -library MTC45000 all_inputs()
set_load 3.5 * load_of(MTC45000/IV/A) all_outputs()
set_load 3.5 * load_of(MTC45000/IV/A) all_inputs()

/* Compile the design and write database */
/* check if everything is setup correctly */
check_design
/* compile the design and optimize, map to target technology */
compile
/* write out the (optimized) database */
write -f db -h -o db_area + main_module + ".db"

check_design

/* Generate reports */

report_area > report_area + main_module + ".area"

report_timing > report_area + main_module + ".time"

report_cell > report_area + main_module + ".cell"

sh date
quit