[Dso-cvs] FPGA/src Latch_A_rtl.vhd,1.4,1.5 Latch_D_rtl.vhd,1.4,1.5

[Gerald Z. <ri...@us...>]

Update of /cvsroot/dso/FPGA/src
In directory sc8-pr-cvs1:/tmp/cvs-serv28799/src

Modified Files:
	Latch_A_rtl.vhd Latch_D_rtl.vhd 
Log Message:



Index: Latch_A_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Latch_A_rtl.vhd,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** Latch_A_rtl.vhd	25 Mar 2003 09:40:59 -0000	1.4
--- Latch_A_rtl.vhd	21 May 2003 12:23:15 -0000	1.5
***************
*** 7,11 ****
  --         Date of Creation:       26-02-2003
  --
! --         Description: Latch for analog input - rtl design
  --                     
  -------------------------------------------------------------------------------
--- 7,11 ----
  --         Date of Creation:       26-02-2003
  --
! --         Description:            Latch for analog input - rtl design
  --                     
  -------------------------------------------------------------------------------
***************
*** 42,63 ****
    -- outputs: Min_o, Avg_o, Max_o
    p_Latch_A: process (Clk, Reset)
-     variable MinStore : std_logic_vector(AnalogWidth -1 downto 0);
-     variable AvgStore : std_logic_vector(AverageWidth-1 downto 0);
-     variable MaxStore : std_logic_vector(AnalogWidth -1 downto 0);
    begin  -- process p_Latch_A
      if Reset = '0' then                 -- asynchronous reset (active low)
!       MinStore := (others => '0');
!       AvgStore := (others => '0');
!       MaxStore := (others => '0');
      elsif Clk'event and Clk = '1' then  -- rising clock edge
        if Latch_i = '1' then  
!         MinStore := Min_i;
!         AvgStore := Avg_i;     
!         MaxStore := Max_i;
        end if;
      end if;
-     Min_o <= MinStore;
-     Avg_o <= AvgStore;
-     Max_o <= MaxStore;
    end process p_Latch_A;
  
--- 42,57 ----
    -- outputs: Min_o, Avg_o, Max_o
    p_Latch_A: process (Clk, Reset)
    begin  -- process p_Latch_A
      if Reset = '0' then                 -- asynchronous reset (active low)
!       Min_o <= (others => '0');
!       Avg_o <= (others => '0');
!       Max_o <= (others => '0');
      elsif Clk'event and Clk = '1' then  -- rising clock edge
        if Latch_i = '1' then  
!         Min_o <= Min_i;
!         Avg_o <= Avg_i;     
!         Max_o <= Max_i;
        end if;
      end if;
    end process p_Latch_A;
  

Index: Latch_D_rtl.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/src/Latch_D_rtl.vhd,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** Latch_D_rtl.vhd	1 Apr 2003 09:13:43 -0000	1.4
--- Latch_D_rtl.vhd	21 May 2003 12:23:15 -0000	1.5
***************
*** 1,14 ****
  -------------------------------------------------------------------------------
  --
! --         Author:                 Sobhi Maher
  --         Filename:               Latch_D_rtl.vhd
  --
  --         Date of Creation:       26-02-2003
  --
! --          
  --                     
  -------------------------------------------------------------------------------
  --
! --    Copyright (C) 2003  Sobhi Maher
  --
  --    This program is free software; you can redistribute it and/or modify
--- 1,15 ----
  -------------------------------------------------------------------------------
  --
! --         Author:                 Gerald Zach
! --
  --         Filename:               Latch_D_rtl.vhd
  --
  --         Date of Creation:       26-02-2003
  --
! --         Description:            Latch for Digital Input - rtl design 
  --                     
  -------------------------------------------------------------------------------
  --
! --    Copyright (C) 2003  Gerald Zach
  --
  --    This program is free software; you can redistribute it and/or modify
***************
*** 38,56 ****
    -- inputs : Clk, Reset, Min_i, Max_i, Latch_i
    -- outputs: Min_o,Max_o
!   Seq0: process (Clk, Reset)
!     variable MinValue : std_logic_vector(DigitalWidth-1 downto 0);  -- last minimum is stored here
!     variable MaxValue : std_logic_vector(DigitalWidth-1 downto 0);  -- last maximum is stored here
!   begin  -- process Seq0
      if Reset = '0' then                 -- asynchronous reset (active low)
!       MinValue := (others => '0');
!       MaxValue := (others => '0');
      elsif Clk'event and Clk = '1' then  -- rising clock edge
        if Latch_i = '1' then  
!         MinValue := Min_i;
!         MaxValue := Max_i;
        end if;
      end if;
!     Min_o <= MinValue;
!     Max_o <= MaxValue;
!   end process Seq0;
  end rtl;
--- 39,53 ----
    -- inputs : Clk, Reset, Min_i, Max_i, Latch_i
    -- outputs: Min_o,Max_o
!   p_Latch_D: process (Clk, Reset)
!   begin  -- process p_Latch_D
      if Reset = '0' then                 -- asynchronous reset (active low)
!       Min_o <= (others => '0');
!       Max_o <= (others => '0');
      elsif Clk'event and Clk = '1' then  -- rising clock edge
        if Latch_i = '1' then  
!         Min_o <= Min_i;
!         Max_o <= Max_i;
        end if;
      end if;
!   end process p_Latch_D;
  end rtl;