[Dso-cvs] FPGA/tb tb_Datapath.vhd,1.5,1.6
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[Dso-cvs] FPGA/tb tb_Datapath.vhd,1.5,1.6
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From: Gerald Z. <ri...@us...> - 2003-05-08 14:48:43
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Update of /cvsroot/dso/FPGA/tb In directory sc8-pr-cvs1:/tmp/cvs-serv4048/FPGA/tb Modified Files: tb_Datapath.vhd Log Message: first 5 tests running, rest not possible: DEMUX_PP must bei modified; Index: tb_Datapath.vhd =================================================================== RCS file: /cvsroot/dso/FPGA/tb/tb_Datapath.vhd,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** tb_Datapath.vhd 30 Apr 2003 11:26:27 -0000 1.5 --- tb_Datapath.vhd 8 May 2003 14:48:39 -0000 1.6 *************** *** 1,358 **** ! ------------------------------------------------------------------------------- ! -- ! -- Author: Gerald Zach ! -- ! -- Filename: tb_CountDown.vhd ! -- ! -- Date of Creation: 09-04-2003 ! -- ! -- Description: Testbench for Datapath ! -- ! ------------------------------------------------------------------------------- ! -- ! -- Copyright (C) 2003 Gerald Zach ! -- ! -- This program is free software; you can redistribute it and/or modify ! -- it under the terms of the GNU General Public License as published by ! -- the Free Software Foundation; either version 2 of the License, or ! -- (at your option) any later version. ! -- ! -- This program is distributed in the hope that it will be useful, ! -- but WITHOUT ANY WARRANTY; without even the implied warranty of ! -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! -- GNU General Public License for more details. ! -- ! -- You should have received a copy of the GNU General Public License ! -- along with this program; if not, write to the Free Software ! -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ! -- ! ------------------------------------------------------------------------------- ! ! library IEEE; ! use IEEE.std_logic_1164.all; ! use IEEE.std_logic_arith.all; ! use IEEE.std_logic_signed."+"; ! use IEEE.std_logic_signed.">"; ! use IEEE.std_logic_signed."<"; ! use IEEE.std_logic_unsigned.conv_integer; ! use IEEE.math_real.all; ! use work.all; ! ! library work; ! use work.types_p.all; ! ! ! entity tb_Datapath is ! generic ( ! AnalogWidth : integer := 10; -- width of analog inputs ! DigitalWidth : integer := 32; -- width of digital inputs ! RAM_Width : integer := 72; -- width of data bus to RAM ! AverageWidth : integer := 36); -- width of averaged input (actually it is a sum) ! end tb_Datapath; ! ! architecture sim of tb_Datapath is ! signal Clk : std_logic := '0'; -- clock for all components ! signal Reset : std_logic := '1'; -- reset for all components LOW ACTIVE!!! ! signal I1 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel1 input ! signal I2 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel2 input ! signal I3 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel3 input ! signal I4 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel4 input ! signal Di : std_logic_vector(DigitalWidth-1 downto 0) := (others => '0'); -- digital inputs ! signal EnAD : std_logic := '0'; -- enable MAM-units at input ! signal ThAD : std_logic := '0'; -- allow inputs to pass MAM input units ! signal Latch : std_logic := '0'; -- latches hold values ! signal MAAM : MAAM_t; -- select Min/Avg1/Avg2/Max to be written to RAM or directed to MUX_uC ! signal RAMdir : std_logic := '0'; -- read/write RAM ! signal EnPP : std_logic := '0'; -- enable PP_Clk ! signal ThPP : std_logic := '0'; -- pass PP-units ! signal uCsel : std_logic_vector(3 downto 0) := (others => '0'); -- select 8 bit words -> output ! signal RAM : std_logic_vector(RAM_Width-1 downto 0); -- RAM values ! signal uC : std_logic_vector(7 downto 0); -- output to uC ! ! signal t_RAM : std_logic_vector(71 downto 0) :=(others => 'Z'); -- varify RAM signal ! signal t_uC : std_logic_vector(7 downto 0); -- varify uC signal ! signal cs : integer := 0; -- for testing routine ! ! constant T2_clk : time := 6.26 ns; -- half period (80MHz) ! ! component Datapath ! generic ( ! AnalogWidth : integer; -- width of analog inputs ! DigitalWidth : integer; -- width of digital inputs ! RAM_Width : integer); -- width of data bus to RAM ! port ( ! CH1_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 1 ! CH2_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 2 ! CH3_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 3 ! CH4_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 4 ! Dig_i : in std_logic_vector(DigitalWidth-1 downto 0); -- digital input channels ! ! RAM_b : inout std_logic_vector(RAM_Width -1 downto 0); -- data path to memory ! ! uC_o : out std_logic_vector(7 downto 0); -- data bus to µC ! ! Clk : in std_logic; -- clock input ! Reset : in std_logic; -- reset input ! ! En_AD_i : in std_logic; -- enable MAMs at input side ! Through_AD_i : in std_logic; -- activate "Through_i" on MAMs at input side ! Latch_AD_i : in std_logic; -- activate Latches at input side ! MAAM_AD_i : in MAAM_t; -- select which group to be routed to RAM ! ! Through_PP_i : in std_logic; -- activate "Through_i" on MAMs at output side ! En_PP_i : in std_logic; -- enable PP_Clk unit ! MAAM_PP_i : in MAAM_t; -- select which group to be routet to the µC ! uC_Select_i : in std_logic_vector( 3 downto 0); -- select 8-bit packet from 72-bit data bus ! ! RAM_Dir_i : in std_logic); -- direction of RAM access (read/write) ! ! --constant AverageWidth : integer: = AverageWidth ; -- width of averaged input (actually it is a sum) ! end component; ! ! begin -- sim ! ! i_Datapath: Datapath ! generic map ( ! AnalogWidth => AnalogWidth, ! DigitalWidth => DigitalWidth, ! RAM_Width => RAM_Width) ! port map ( ! CH1_i => I1, ! CH2_i => I2, ! CH3_i => I3, ! CH4_i => I4, ! Dig_i => Di, ! RAM_b => RAM, ! uC_o => uC, ! Clk => Clk, ! Reset => Reset, ! En_AD_i => EnAD, ! Through_AD_i => ThAD, ! Latch_AD_i => Latch, ! MAAM_AD_i => MAAM , ! En_PP_i => EnPP, ! Through_PP_i => ThPP, ! MAAM_PP_i => MAAM , ! uC_Select_i => uCsel, ! RAM_Dir_i => RAMdir); ! ! -- purpose: generate Clk signal ! -- type : combinational ! -- inputs : ! -- outputs: Clk ! p_Clk: process ! begin -- process p_Clk ! Clk <= not Clk; ! wait for T2_clk; ! end process p_Clk; ! ! -- purpose: generate input signals ! -- type : combinational ! -- inputs : ! -- outputs: I1,I2,I3,I4,Di ! p_input: process ! variable count : integer := -50; -- count variable ! variable incdec : integer := 1; -- increment/decrement ! begin -- process p_input ! I1 <= conv_std_logic_vector(5*count,AnalogWidth); ! I3 <= conv_std_logic_vector(-5*count,AnalogWidth); ! I2 <= conv_std_logic_vector(count, AnalogWidth); ! I4 <= conv_std_logic_vector(-count, AnalogWidth); ! Di <= conv_std_logic_vector(count, DigitalWidth); ! ! count := count + incdec; ! if count > 50 then ! count := 50; ! incdec := -1; ! end if; ! if count < -50 then ! count := -50; ! incdec := 1; ! end if; ! ! wait for 10 ns; ! end process p_input; ! ! ! -- purpose: test datapath ! -- type : combinational ! -- inputs : ! -- outputs: ! p_Test: process ! ! begin -- process p_Test ! ! -- 1) test input(4 analog channels + digital channel) -> RAM ! -- 1.1) trough at highest rate ! ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! wait for 20 ns; ! cs <= 1; ! EnAD <= '1'; ! ThAD <= '1'; ! Latch <= '1'; ! MAAM <= MAAM_Min; ! RAMdir <= '0'; ! wait for 1000 ns; ! ! -- 1.2) sampling at lower bitrate ! ! RamDir <= '0'; ! EnAD <= '1'; ! ThAD <= '0'; ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! Cs <= 2; ! wait for 20 ns; ! Latch <= '1'; ! wait for 20*T2_Clk; ! Latch <= '0'; ! wait for T2_Clk; ! wait on Clk; ! MAAM <= MAAM_Min; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Max; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Avg1; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Avg2; ! wait for 2*T2_Clk; ! wait for 100 ns; ! ! -- 2) test RAM -> output(uC) ! -- 2.1) stored trough signal, trough PP units ! ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! wait for 20 ns; ! cs <= 3; ! EnAD <= '0'; ! ThAD <= '0'; ! Latch <= '0'; ! EnPP <= '1'; ! ThPP <= '1'; ! MAAM <= MAAM_Max; ! RAMdir <= '1'; ! wait for T2_Clk; ! RAM <= "101110000110111010101111100011010101111011000011101110010101011101001011"; ! wait on Clk; ! for i in 0 to 8 loop ! uCsel <= conv_std_logic_vector(i,4); ! wait for 2*T2_Clk; ! end loop; -- i ! RAM <= (others => 'Z'); ! ! ! ! end process p_Test; ! ! -- purpose: varify output signals ! -- type : combinational ! -- inputs : RAM ! -- outputs: ! p_varify: process (RAM,uC) ! begin -- process p_varify ! if (cs <3 and cs > 0) then ! assert RAM = t_RAM report "Signals do not match, component NOT OK!" severity WARNING; ! else ! assert uC = t_uC report "Signals do not match, component NOT OK!" severity WARNING; ! end if; ! end process p_varify; ! ! -- purpose: generating test signal t_RAM ! -- type : combinational ! -- inputs : Clk,Reset ! -- outputs: t_RAM ! p_genTest: process (Clk, Reset) ! variable help : std_logic_vector(71 downto 0); ! variable h_min, o_min : std_logic_vector(71 downto 0); ! variable h_max, o_max : std_logic_vector(71 downto 0); ! variable h_avg1,o_avg1 : std_logic_vector(71 downto 0); ! variable h_avg2,o_avg2 : std_logic_vector(71 downto 0); ! variable llc : integer := 0; -- loop count variable ! begin -- process p_genTest ! if Reset = '0' then -- asynchronous reset (active low) ! t_RAM <= (others => '0'); ! t_uC <= (others => '0'); ! help := (others => '0'); ! h_min := (others => '0'); ! h_max := (others => '0'); ! h_avg1 := (others => '0'); ! h_avg2 := (others => '0'); ! o_min := (others => '0'); ! o_max := (others => '0'); ! o_avg1 := (others => '0'); ! o_avg2 := (others => '0'); ! ! ! elsif Clk'event and Clk = '1' then -- rising clock edge ! case cs is ! when 1 => help(71 downto 40) := Di; ! help(39 downto 30) := I4; ! help(29 downto 20) := I3; ! help(19 downto 10) := I2; ! help( 9 downto 0) := I1; ! t_RAM <= help after 2*T2_Clk; ! when 2 => if llc=1 then ! ! if IEEE.std_logic_signed."<"(I1'Delayed(2*T2_Clk),h_min(9 downto 0)) then ! h_min(9 downto 0) := I1'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I2'Delayed(2*T2_Clk),h_min(19 downto 10)) then ! h_min(19 downto 10) := I2'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I3'Delayed(2*T2_Clk),h_min(29 downto 20)) then ! h_min(29 downto 20) := I3'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I4'Delayed(2*T2_Clk),h_min(39 downto 30)) then ! h_min(39 downto 30) := I4'Delayed(2*T2_Clk); ! end if; ! h_min(71 downto 40) := h_min(71 downto 40) and Di'Delayed(2*T2_Clk); ! ! if IEEE.std_logic_signed.">"(I1'Delayed(2*T2_Clk),h_max(9 downto 0)) then ! h_max(9 downto 0) := I1'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I2'Delayed(2*T2_Clk),h_max(19 downto 10)) then ! h_max(19 downto 10) := I2'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I3'Delayed(2*T2_Clk),h_max(29 downto 20)) then ! h_max(29 downto 20) := I3'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I4'Delayed(2*T2_Clk),h_max(39 downto 30)) then ! h_max(39 downto 30) := I4'Delayed(2*T2_Clk); ! end if; ! h_max(71 downto 40) := h_max(71 downto 40) or Di'Delayed(2*T2_Clk); ! ! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I2'Delayed(2*T2_Clk); ! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I1'Delayed(2*T2_Clk); ! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I4'Delayed(2*T2_Clk); ! h_avg2(35 downto 0) := h_avg2(35 downto 0) + I3'Delayed(2*T2_Clk); ! ! if Latch='1' then ! o_min := h_min; ! o_max := h_max; ! o_avg1:= h_avg1; ! o_avg2:= h_avg2; ! end if; ! ! case MAAM is ! when MAAM_Min => t_RAM <= o_min ; ! when MAAM_Max => t_RAM <= o_max ; ! when MAAM_Avg1=> t_RAM <= o_avg1; ! when MAAM_Avg2=> t_RAM <= o_avg2; ! end case; ! else ! llc:=1; -- one period delay ! end if; ! when 3 => t_uC <= RAM((conv_integer(uCsel)+1)*8-1 downto conv_integer(uCsel)*8); ! when others => null; ! end case; ! ! end if; ! end process p_genTest; ! ! end sim; --- 1,545 ---- ! ------------------------------------------------------------------------------- ! -- ! -- Author: Gerald Zach ! -- ! -- Filename: tb_CountDown.vhd ! -- ! -- Date of Creation: 09-04-2003 ! -- ! -- Description: Testbench for Datapath ! -- ! ------------------------------------------------------------------------------- ! -- ! -- Copyright (C) 2003 Gerald Zach ! -- ! -- This program is free software; you can redistribute it and/or modify ! -- it under the terms of the GNU General Public License as published by ! -- the Free Software Foundation; either version 2 of the License, or ! -- (at your option) any later version. ! -- ! -- This program is distributed in the hope that it will be useful, ! -- but WITHOUT ANY WARRANTY; without even the implied warranty of ! -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! -- GNU General Public License for more details. ! -- ! -- You should have received a copy of the GNU General Public License ! -- along with this program; if not, write to the Free Software ! -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ! -- ! ------------------------------------------------------------------------------- ! ! library IEEE; ! use IEEE.std_logic_1164.all; ! use IEEE.std_logic_arith.all; ! use IEEE.std_logic_signed."+"; ! use IEEE.std_logic_signed.">"; ! use IEEE.std_logic_signed."<"; ! use IEEE.std_logic_unsigned.conv_integer; ! use IEEE.math_real.all; ! use work.all; ! ! library work; ! use work.types_p.all; ! ! ! entity tb_Datapath is ! generic ( ! AnalogWidth : integer := 10; -- width of analog inputs ! DigitalWidth : integer := 32; -- width of digital inputs ! RAM_Width : integer := 72; -- width of data bus to RAM ! AverageWidth : integer := 36); -- width of averaged input (actually it is a sum) ! end tb_Datapath; ! ! architecture sim of tb_Datapath is ! signal Clk : std_logic := '0'; -- clock for all components ! signal Reset : std_logic := '1'; -- reset for all components LOW ACTIVE!!! ! signal I1 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel1 input ! signal I2 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel2 input ! signal I3 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel3 input ! signal I4 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel4 input ! signal Di : std_logic_vector(DigitalWidth-1 downto 0) := (others => '0'); -- digital inputs ! signal EnAD : std_logic := '0'; -- enable MAM-units at input ! signal ThAD : std_logic := '0'; -- allow inputs to pass MAM input units ! signal Latch : std_logic := '0'; -- latches hold values ! signal MAAM : MAAM_t; -- select Min/Avg1/Avg2/Max to be written to RAM or directed to MUX_uC ! signal RAMdir : std_logic := '0'; -- read/write RAM ! signal EnPP : std_logic := '0'; -- enable PP_Clk ! signal ThPP : std_logic := '0'; -- pass PP-units ! signal uCsel : std_logic_vector(3 downto 0) := (others => '0'); -- select 8 bit words -> output ! signal RAM : std_logic_vector(RAM_Width-1 downto 0); -- RAM values ! signal uC : std_logic_vector(7 downto 0); -- output to uC ! ! -- signals especially for testing ! signal t_RAM : std_logic_vector(71 downto 0) :=(others => 'Z'); -- varify RAM signal ! signal t_uC : std_logic_vector(7 downto 0); -- varify uC signal ! signal TestState : Test_t := IdlePrep; -- for testing routine ! ! constant T2_clk : time := 6.25 ns; -- half period (80MHz) ! ! component Datapath ! generic ( ! AnalogWidth : integer; -- width of analog inputs ! DigitalWidth : integer; -- width of digital inputs ! RAM_Width : integer); -- width of data bus to RAM ! port ( ! CH1_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 1 ! CH2_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 2 ! CH3_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 3 ! CH4_i : in std_logic_vector(AnalogWidth -1 downto 0); -- analog input channel 4 ! Dig_i : in std_logic_vector(DigitalWidth-1 downto 0); -- digital input channels ! ! RAM_b : inout std_logic_vector(RAM_Width -1 downto 0); -- data path to memory ! ! uC_o : out std_logic_vector(7 downto 0); -- data bus to µC ! ! Clk : in std_logic; -- clock input ! Reset : in std_logic; -- reset input ! ! En_AD_i : in std_logic; -- enable MAMs at input side ! Through_AD_i : in std_logic; -- activate "Through_i" on MAMs at input side ! Latch_AD_i : in std_logic; -- activate Latches at input side ! MAAM_AD_i : in MAAM_t; -- select which group to be routed to RAM ! ! Through_PP_i : in std_logic; -- activate "Through_i" on MAMs at output side ! En_PP_i : in std_logic; -- enable PP_Clk unit ! MAAM_PP_i : in MAAM_t; -- select which group to be routet to the µC ! uC_Select_i : in std_logic_vector( 3 downto 0); -- select 8-bit packet from 72-bit data bus ! ! RAM_Dir_i : in std_logic); -- direction of RAM access (read/write) ! ! end component; ! ! begin -- sim ! ! i_Datapath: Datapath ! generic map ( ! AnalogWidth => AnalogWidth, ! DigitalWidth => DigitalWidth, ! RAM_Width => RAM_Width) ! port map ( ! CH1_i => I1, ! CH2_i => I2, ! CH3_i => I3, ! CH4_i => I4, ! Dig_i => Di, ! RAM_b => RAM, ! uC_o => uC, ! Clk => Clk, ! Reset => Reset, ! En_AD_i => EnAD, ! Through_AD_i => ThAD, ! Latch_AD_i => Latch, ! MAAM_AD_i => MAAM , ! En_PP_i => EnPP, ! Through_PP_i => ThPP, ! MAAM_PP_i => MAAM , ! uC_Select_i => uCsel, ! RAM_Dir_i => RAMdir); ! ! -- purpose: generate Clk signal ! -- type : combinational ! -- inputs : ! -- outputs: Clk ! p_Clk: process ! begin -- process p_Clk ! Clk <= not Clk; ! wait for T2_clk; ! end process p_Clk; ! ! -- purpose: generate input signals ! -- type : combinational ! -- inputs : ! -- outputs: I1,I2,I3,I4,Di ! p_input: process ! variable count : integer := -50; -- count variable ! variable incdec : integer := 1; -- increment/decrement ! begin -- process p_input ! I1 <= conv_std_logic_vector(5*count,AnalogWidth); ! -- I3 <= conv_std_logic_vector(-5*count,AnalogWidth); ! -- I2 <= conv_std_logic_vector(count, AnalogWidth); ! -- I4 <= conv_std_logic_vector(-count, AnalogWidth); ! Di <= conv_std_logic_vector(count, DigitalWidth); ! ! ! I2 <= conv_std_logic_vector(5*count,AnalogWidth); ! I3 <= conv_std_logic_vector(5*count,AnalogWidth); ! I4 <= conv_std_logic_vector(5*count,AnalogWidth); ! ! count := count + incdec; ! if count > 50 then ! count := 50; ! incdec := -1; ! end if; ! if count < -50 then ! count := -50; ! incdec := 1; ! end if; ! ! wait for 10 ns; ! end process p_input; ! ! ! -- purpose: test datapath ! -- type : combinational ! -- inputs : ! -- outputs: ! p_Test: process ! ! begin -- process p_Test ! ! RAM <= (others => 'Z'); ! ! -- 1) test input(4 analog channels + digital channel) -> RAM ! -- 1.1) trough at highest rate ! ! ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! wait for 20 ns; ! TestState <= Test1; ! EnAD <= '1'; ! ThAD <= '1'; ! Latch <= '1'; ! MAAM <= MAAM_Min; ! RAMdir <= '0'; ! wait for 1000 ns; ! ! -- 1.2) sampling at lower bitrate ! ! RamDir <= '0'; ! EnAD <= '1'; ! ThAD <= '0'; ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! TestState <= Test2; ! wait for 20 ns; ! Latch <= '1'; ! wait for 20*T2_Clk; ! Latch <= '0'; ! wait for T2_Clk; ! wait on Clk; ! MAAM <= MAAM_Min; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Max; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Avg1; ! wait for 2*T2_Clk; ! MAAM <= MAAM_Avg2; ! wait for 2*T2_Clk; ! wait for 100 ns; ! ! -- 2) test RAM -> output(uC) ! -- 2.1) stored trough signal, trough PP units ! ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! wait for 20 ns; ! TestState <= Test3; ! EnAD <= '0'; ! ThAD <= '0'; ! Latch <= '0'; ! EnPP <= '1'; ! ThPP <= '1'; ! MAAM <= MAAM_Min; ! RAMdir <= '1'; ! wait for T2_Clk; ! RAM <= "101110000110111010101111100011010101111011000011101110010101011101001011"; ! wait on Clk; ! for i in 0 to 8 loop ! uCsel <= conv_std_logic_vector(i,4); ! wait for 2*T2_Clk; ! end loop; -- i ! ! -- 2.2) stored MAM signal, through PP units ! ! TestState <= IdlePrep; ! uCsel <= "0000"; ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! wait for 20 ns; ! EnAD <= '0'; ! ThAD <= '0'; ! Latch <= '0'; ! EnPP <= '1'; ! ThPP <= '1'; ! RAMdir <= '1'; ! RAM <= "101110000110111010101111100011010101111011000011101110010101011101001011"; ! wait for T2_Clk; ! wait on Clk; ! for j in 1 to 4 loop ! case j is ! when 1 => MAAM <= MAAM_Min; ! when 2 => MAAM <= MAAM_Avg1; ! when 3 => MAAM <= MAAM_Avg2; ! when 4 => MAAM <= MAAM_Max; ! when others => null; ! end case; ! wait for T2_Clk; ! TestState <= Test4; ! wait for T2_Clk; ! for i in 0 to 8 loop ! uCsel <= conv_std_logic_vector(i,4); ! wait for 2*T2_Clk; ! end loop; -- i ! TestState <= IdlePrep; ! end loop; -- j ! --RAM <= (others => 'Z'); ! wait for 50 ns; ! ! -- 2.3) stored through signal, PP for 10 samples ! -- test for MIN ! TestState <= IdlePrep; ! EnPP <= '0'; ! MAAM <= MAAM_Min; ! uCsel <= "0000"; ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! TestState <= Test5; ! wait for 20 ns; ! EnAD <= '0'; ! ThAD <= '0'; ! Latch <= '0'; ! EnPP <= '1'; ! ThPP <= '0'; ! RAMdir <= '1'; ! wait on Clk; ! for i in 1 to 10 loop ! RAM( 9 downto 0) <= I1; ! RAM(19 downto 10) <= I2; ! RAM(29 downto 20) <= I3; ! RAM(39 downto 30) <= I4; ! RAM(71 downto 40) <= Di; ! wait for 2*T2_Clk; ! end loop; -- i ! EnPP <= '0'; ! wait for T2_Clk; ! for i in 0 to 8 loop ! uCsel <= conv_std_logic_vector(i,4); ! wait for 2*T2_Clk; ! end loop; -- i ! TestState <= IdlePrep; ! RAM <= (others => 'Z'); ! ! -- test for MAX ! TestState <= IdlePrep; ! EnPP <= '0'; ! MAAM <= MAAM_Max; ! uCsel <= "0000"; ! Reset <= '0'; ! wait for 20 ns; ! Reset <= '1'; ! TestState <=Test5; ! wait for 20 ns; ! EnAD <= '0'; ! ThAD <= '0'; ! Latch <= '0'; ! EnPP <= '1'; ! ThPP <= '0'; ! RAMdir <= '1'; ! wait on Clk; ! for i in 1 to 10 loop ! RAM( 9 downto 0) <= I1; ! RAM(19 downto 10) <= I2; ! RAM(29 downto 20) <= I3; ! RAM(39 downto 30) <= I4; ! RAM(71 downto 40) <= Di; ! wait for 2*T2_Clk; ! end loop; -- i ! EnPP <= '0'; ! wait for T2_Clk; ! for i in 0 to 8 loop ! uCsel <= conv_std_logic_vector(i,4); ! wait for 2*T2_Clk; ! end loop; -- i ! TestState <= IdlePrep; ! ------------------------------------------------------------------------------- ! -- tests for Avg not possible: DEMUX_PP does not allow this configuration !!! ! ------------------------------------------------------------------------------- ! wait for 100 ns; ! ! -- 2.4) stored Min/Avg1/Avg2/Max signal, PP for 10 samples ! ! -- test not possible: DEMUX_PP does not allow this configuration! ! ! end process p_Test; ! ! ! ! -- purpose: verify output signals ! -- type : combinational ! -- inputs : RAM ! -- outputs: ! p_verify: process (RAM,uC) ! begin -- process p_varify ! case TestState is ! when Test1 => assert RAM = t_RAM report "Signals do not match, component NOT OK!" severity WARNING; ! when Test2 => assert RAM = t_RAM report "Signals do not match, component NOT OK!" severity WARNING; ! when Test3 => assert uC = t_uC report "Signals do not match, component NOT OK!" severity WARNING; ! when Test4 => assert uC = t_uC report "Signals do not match, component NOT OK!" severity WARNING; ! when Test5 => if EnPP = '0' then ! assert uC = t_uC report "Signals do not match, component NOT OK!" severity WARNING; ! end if; ! when Test6 => assert uC = t_uC report "Signals do not match, component NOT OK!" severity WARNING; ! when others => null; ! end case; ! end process p_verify; ! ! ! -- purpose: generating test signal t_RAM ! -- type : combinational ! -- inputs : Clk,Reset ! -- outputs: t_RAM ! p_genTest: process (Clk, Reset) ! variable help : std_logic_vector(71 downto 0); ! variable h_min, o_min : std_logic_vector(71 downto 0); ! variable h_max, o_max : std_logic_vector(71 downto 0); ! variable h_avg1,o_avg1 : std_logic_vector(71 downto 0); ! variable h_avg2,o_avg2 : std_logic_vector(71 downto 0); ! variable llc : integer := 0; -- loop count variable ! begin -- process p_genTest ! if Reset = '0' then -- asynchronous reset (active low) ! t_RAM <= (others => '0'); ! t_uC <= (others => '0'); ! help := (others => '0'); ! h_min := (others => '0'); ! h_max := (others => '0'); ! h_avg1 := (others => '0'); ! h_avg2 := (others => '0'); ! o_min := (others => '0'); ! o_max := (others => '0'); ! o_avg1 := (others => '0'); ! o_avg2 := (others => '0'); ! ! ! elsif Clk'event and Clk = '1' then -- rising clock edge ! case TestState is ! when Test1 => help(71 downto 40) := Di; ! help(39 downto 30) := I4; ! help(29 downto 20) := I3; ! help(19 downto 10) := I2; ! help( 9 downto 0) := I1; ! t_RAM <= help after 2*T2_Clk; ! when Test2 => if llc=1 then ! ! if IEEE.std_logic_signed."<"(I1'Delayed(2*T2_Clk),h_min(9 downto 0)) then ! h_min(9 downto 0) := I1'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I2'Delayed(2*T2_Clk),h_min(19 downto 10)) then ! h_min(19 downto 10) := I2'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I3'Delayed(2*T2_Clk),h_min(29 downto 20)) then ! h_min(29 downto 20) := I3'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I4'Delayed(2*T2_Clk),h_min(39 downto 30)) then ! h_min(39 downto 30) := I4'Delayed(2*T2_Clk); ! end if; ! h_min(71 downto 40) := h_min(71 downto 40) and Di'Delayed(2*T2_Clk); ! ! if IEEE.std_logic_signed.">"(I1'Delayed(2*T2_Clk),h_max(9 downto 0)) then ! h_max(9 downto 0) := I1'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I2'Delayed(2*T2_Clk),h_max(19 downto 10)) then ! h_max(19 downto 10) := I2'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I3'Delayed(2*T2_Clk),h_max(29 downto 20)) then ! h_max(29 downto 20) := I3'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I4'Delayed(2*T2_Clk),h_max(39 downto 30)) then ! h_max(39 downto 30) := I4'Delayed(2*T2_Clk); ! end if; ! h_max(71 downto 40) := h_max(71 downto 40) or Di'Delayed(2*T2_Clk); ! ! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I2'Delayed(2*T2_Clk); ! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I1'Delayed(2*T2_Clk); ! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I4'Delayed(2*T2_Clk); ! h_avg2(35 downto 0) := h_avg2(35 downto 0) + I3'Delayed(2*T2_Clk); ! ! if Latch='1' then ! o_min := h_min; ! o_max := h_max; ! o_avg1:= h_avg1; ! o_avg2:= h_avg2; ! end if; ! ! case MAAM is ! when MAAM_Min => t_RAM <= o_min ; ! when MAAM_Max => t_RAM <= o_max ; ! when MAAM_Avg1=> t_RAM <= o_avg1; ! when MAAM_Avg2=> t_RAM <= o_avg2; ! end case; ! else ! llc:=1; -- one period delay ! end if; ! when Test3 => t_uC <= RAM((conv_integer(uCsel)+1)*8-1 downto conv_integer(uCsel)*8); ! when Test4 => t_uC <= RAM((conv_integer(uCsel)+1)*8-1 downto conv_integer(uCsel)*8); ! llc := 0; ! when Test5 => if llc =1 then ! if EnPP = '1' then ! ! if IEEE.std_logic_signed."<"(I1'Delayed(2*T2_Clk),h_min(9 downto 0)) then ! h_min(9 downto 0) := I1'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I2'Delayed(2*T2_Clk),h_min(19 downto 10)) then ! h_min(19 downto 10) := I2'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I3'Delayed(2*T2_Clk),h_min(29 downto 20)) then ! h_min(29 downto 20) := I3'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed."<"(I4'Delayed(2*T2_Clk),h_min(39 downto 30)) then ! h_min(39 downto 30) := I4'Delayed(2*T2_Clk); ! end if; ! h_min(71 downto 40) := h_min(71 downto 40) and Di'Delayed(2*T2_Clk); ! ! if IEEE.std_logic_signed.">"(I1'Delayed(2*T2_Clk),h_max(9 downto 0)) then ! h_max(9 downto 0) := I1'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I2'Delayed(2*T2_Clk),h_max(19 downto 10)) then ! h_max(19 downto 10) := I2'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I3'Delayed(2*T2_Clk),h_max(29 downto 20)) then ! h_max(29 downto 20) := I3'Delayed(2*T2_Clk); ! end if; ! if IEEE.std_logic_signed.">"(I4'Delayed(2*T2_Clk),h_max(39 downto 30)) then ! h_max(39 downto 30) := I4'Delayed(2*T2_Clk); ! end if; ! h_max(71 downto 40) := h_max(71 downto 40) or Di'Delayed(2*T2_Clk); ! ! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I2'Delayed(2*T2_Clk); ! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I1'Delayed(2*T2_Clk); ! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I4'Delayed(2*T2_Clk); ! h_avg2(35 downto 0) := h_avg2(35 downto 0) + I3'Delayed(2*T2_Clk); ! ! else ! o_min := h_min; ! o_max := h_max; ! o_avg1:= h_avg1; ! o_avg2:= h_avg2; ! end if; ! else ! llc:=1; ! end if; ! ! case MAAM is ! when MAAM_Min => t_RAM <= o_min ; ! when MAAM_Max => t_RAM <= o_max ; ! when MAAM_Avg1=> t_RAM <= o_avg1; ! when MAAM_Avg2=> t_RAM <= o_avg2; ! end case; ! ! if EnPP='0' then ! t_uC <= t_RAM((conv_integer(uCsel)+1)*8-1 downto conv_integer(uCsel)*8); ! end if; ! ! -- when Test6 =>; ! ! when others => null; ! end case; ! end if; ! end process p_genTest; ! ! end sim; |
