[Dso-cvs] FPGA/tb tb_Datapath.vhd,1.3,1.4
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[Dso-cvs] FPGA/tb tb_Datapath.vhd,1.3,1.4
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From: Gerald Z. <ri...@us...> - 2003-04-29 14:28:10
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Update of /cvsroot/dso/FPGA/tb
In directory sc8-pr-cvs1:/tmp/cvs-serv456/FPGA/tb
Modified Files:
tb_Datapath.vhd
Log Message:
Index: tb_Datapath.vhd
===================================================================
RCS file: /cvsroot/dso/FPGA/tb/tb_Datapath.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** tb_Datapath.vhd 18 Apr 2003 09:27:32 -0000 1.3
--- tb_Datapath.vhd 29 Apr 2003 14:28:05 -0000 1.4
***************
*** 50,54 ****
architecture sim of tb_Datapath is
signal Clk : std_logic := '0'; -- clock for all components
! signal Reset : std_logic := '0'; -- reset for all components
signal I1 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel1 input
signal I2 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel2 input
--- 50,54 ----
architecture sim of tb_Datapath is
signal Clk : std_logic := '0'; -- clock for all components
! signal Reset : std_logic := '1'; -- reset for all components LOW ACTIVE!!!
signal I1 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel1 input
signal I2 : std_logic_vector(AnalogWidth -1 downto 0) := (others => '0'); -- channel2 input
***************
*** 155,158 ****
--- 155,159 ----
I4 <= conv_std_logic_vector(-count, AnalogWidth);
Di <= conv_std_logic_vector(count, DigitalWidth);
+
count := count + 1;
if count > 50 then
***************
*** 174,181 ****
-- 1.1) trough at highest rate
- Reset <= '1';
- wait for 20 ns;
Reset <= '0';
wait for 20 ns;
cs <= 1;
EnAD <= '1';
--- 175,182 ----
-- 1.1) trough at highest rate
Reset <= '0';
wait for 20 ns;
+ Reset <= '1';
+ wait for 20 ns;
cs <= 1;
EnAD <= '1';
***************
*** 187,198 ****
-- 1.2) sampling at lower bitrate
! Reset <= '1';
! wait for 20 ns;
! Reset <= '0';
! wait for 20 ns;
! cs <= 2;
RamDir <= '0';
EnAD <= '1';
ThAD <= '0';
Latch <= '1';
wait for 20*T2_Clk;
--- 188,200 ----
-- 1.2) sampling at lower bitrate
!
RamDir <= '0';
EnAD <= '1';
ThAD <= '0';
+ Reset <= '0';
+ wait for 20 ns;
+ Reset <= '1';
+ Cs <= 2;
+ wait for 20 ns;
Latch <= '1';
wait for 20*T2_Clk;
***************
*** 207,211 ****
MAAM <= MAAM_Avg2;
wait for 2*T2_Clk;
!
--- 209,213 ----
MAAM <= MAAM_Avg2;
wait for 2*T2_Clk;
! wait for 100 ns;
***************
*** 249,292 ****
elsif Clk'event and Clk = '1' then -- rising clock edge
case cs is
! when 1 => help(71 downto 62) := I1;
! help(61 downto 52) := I2;
! help(51 downto 42) := I3;
! help(41 downto 32) := I4;
! help(31 downto 0) := Di;
! t_RAM <= help after 2*T2_Clk;
! when 2 => if I1 < h_min(71 downto 62) then
! h_min(71 downto 62) := I1;
! end if;
! if I2 < h_min(61 downto 52) then
! h_min(61 downto 52) := I2;
! end if;
! if I3 < h_min(51 downto 42) then
! h_min(51 downto 42) := I3;
! end if;
! if I4 < h_min(41 downto 32) then
! h_min(41 downto 32) := I4;
! end if;
! h_min(31 downto 0) := h_min(31 downto 0) and Di;
! if I1 > h_max(71 downto 62) then
! h_min(71 downto 62) := I1;
! end if;
! if I2 > h_max(61 downto 52) then
! h_min(61 downto 52) := I2;
! end if;
! if I3 > h_max(51 downto 42) then
! h_min(51 downto 42) := I3;
! end if;
! if I4 > h_max(41 downto 32) then
! h_min(41 downto 32) := I4;
! end if;
! h_max(31 downto 0) := h_max(31 downto 0) or Di;
! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I1;
! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I2;
! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I3;
! h_avg2(35 downto 0) := h_avg2(36 downto 0) + I4;
! if Latch='1' then
o_min := h_min;
o_max := h_max;
--- 251,295 ----
elsif Clk'event and Clk = '1' then -- rising clock edge
case cs is
! when 1 => help(71 downto 40) := Di;
! help(39 downto 30) := I4;
! help(29 downto 20) := I3;
! help(19 downto 10) := I2;
! help( 9 downto 0) := I1;
! t_RAM <= help after 2*T2_Clk;
! when 2 =>
! if I1 < h_min(9 downto 0) then
! h_min(9 downto 0) := I1;
! end if;
! if I2 < h_min(19 downto 10) then
! h_min(19 downto 10) := I2;
! end if;
! if I3 < h_min(29 downto 20) then
! h_min(29 downto 20) := I3;
! end if;
! if I4 < h_min(39 downto 30) then
! h_min(39 downto 30) := I4;
! end if;
! h_min(71 downto 40) := h_min(31 downto 0) and Di;
! if I1 > h_max(9 downto 0) then
! h_min(9 downto 0) := I1;
! end if;
! if I2 > h_max(19 downto 10) then
! h_min(19 downto 10) := I2;
! end if;
! if I3 > h_max(29 downto 20) then
! h_min(29 downto 20) := I3;
! end if;
! if I4 > h_max(39 downto 30) then
! h_min(39 downto 30) := I4;
! end if;
! h_max(71 downto 40) := h_max(31 downto 0) or Di;
! h_avg1(71 downto 36) := h_avg1(71 downto 36) + I2;
! h_avg1(35 downto 0) := h_avg1(35 downto 0) + I1;
! h_avg2(71 downto 36) := h_avg2(71 downto 36) + I4;
! h_avg2(35 downto 0) := h_avg2(35 downto 0) + I3;
! if Latch='0' then
o_min := h_min;
o_max := h_max;
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