Search Results for "drcom-for-linux" - Page 3
Sort By:
Showing 111 open source projects for "drcom-for-linux"
View related business solutions-
Resolve Support Tickets 2x Faster with ServoDeskWhat if You Could Automate 90% of Your Repetitive Tasks in Under 30 Days? At ServoDesk, we help businesses like yours automate operations with AI, allowing you to cut service times in half and increase productivity by 25% - without hiring more staff.
-
Our Free Plans just got better! | Auth0You asked, we delivered! Auth0 is excited to expand our Free and Paid plans to include more options so you can focus on building, deploying, and scaling applications without having to worry about your security. Auth0 now, thank yourself later.
-
1
smPla
SystemVerilog module to substitute Verilog PLA system tasks.
SystemVerilog module that models the following PLA system tasks of Verilog: $a/sync$and$array $a/sync$nand$array $a/sync$or$array $a/sync$nor$array $a/sync$and$plane $a/sync$nand$plane $a/sync$or$plane $a/sync$nor$plane. -
2
Application de fines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
-
3
AVRILOS
Simple AVR OS
A simple Embedded System Framework that allows rapid development of applications build for AVR family. System is based on a super-loop architecture with check and skip (no-wait) flag event driver system. Supports: UART, SysTick Timer, ADC, SPI, EEPROM, PWM. Also supports: Xilinx FPGA configuration, FPGA SSI interface, smart card reader etc. Tested partially (different modules in each case) on ATMega163/16/32/323/8. Awards CodeProject 2010, Third Prize, Hardware and Device... -
4
vcd2svg can parse Value Change Dump (VCD) files and draw an impulse diagram using Scalable Vector Graphics (SVG). It works together with the GHDL open-source simulator.
-
The Easy Way To Build A Referral ProgramReferral Factory offers over 1000 pre-built referral program templates you can use as your own, or you can build your own referral program from scratch. You get unlimited referral campaigns on all plans, and brilliant support from their team of referral marketing experts.
-
5
xswifs stands for: cross SoftWare Interfaces. This project provide examples (snippets) for interfacing various software tools and languages with various mechanism. It has been created to help in HW/SW co-simulation and to provide benchmarks.
-
6
A free VHDL IPs for general purpose FPGA developpement. Need GRLIB to work properly, to setup see README.
-
7
This library supports interoperability between components written for different verification methodologies such as VMM and OVM. This is maintained by the Accellera Verification Intellectual Property Technical Subcommittee.
-
8
-
9
-
Google AI Studio | Gemini API | Google for DevelopersGoogle AI Studio is a comprehensive, web-based development environment that democratizes access to Google's cutting-edge AI models, notably the Gemini family, enabling a broad spectrum of users to explore and build innovative applications. This platform facilitates rapid prototyping by providing an intuitive interface for prompt engineering, allowing developers to meticulously craft and refine their interactions with AI. Beyond basic experimentation, AI Studio supports the seamless integration of AI capabilities into diverse projects, from simple chatbots to complex data analysis tools. Users can rigorously test different prompts, observe model behaviors, and iteratively refine their AI-driven solutions within a collaborative and user-friendly environment. This empowers developers to push the boundaries of AI application development, fostering creativity and accelerating the realization of AI-powered solutions.
-
10
vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.
-
11
The foosball game is implemented in VHDL for use with the Altera DE2 FPGA board with the visual interface in a VGA monitor and input interface in a PS/2 keyboard.
-
12
This card will capture High Definition Video 1280x720 at 30fps, and soon be capable of 60fps and maybe even 1080p. This is a hardware project so source code, RTL, and board CAD files will be involved. All IC's and parts should be easily available.
-
13
-
14
This project implements an On Screen Display for FPV (First Person View) for RC planes. Sends telemetry data from GPS & sensors embebed with video information.
-
15
Writing Testbenches for FPGA/ASIC design is always a very fastidious and boring task. This project helps any FPGA/ASIC designer by providing a full RTL test environment with C support.
-
16
A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.
-
17
The HDL Complexity Tool parses large complex hardware projects' source code to produce useful complexity results. GOALS: 1)Practical, effective and simple 2) Integrates with existing design flows 3) Used on real projects 4) Based on existing research
-
18
OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.
-
19
Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. ZhangDong & KangCai
-
20
A command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The code is written in C for Win32 platform
-
21
This project's goal is to provide a simple but extendable SOC (System On Chip) that can be loaded into an FPGA in order to quickly test custom coprocessors and evaluate their robustness against SCA (Side Channel Attacks) or others physical attacks.
-
22
Custom Architecture Generator Tool is a software based on the Netbeans Platform, the main purpose is to accelerate the embedded system realisation with a high level description: VHDL code,C2VHDL conversion,Quartus project generation,real time application
-
23
VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book
-
24
-
25
The goal of this project is to develop an easily modifiable combination of VHDL firmware and LabView drivers for use with laboratory automation control and data acquisition using Terasic's DE2 board and the ISP1362 USB interface chip.
