Application defines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.

Features

  • This is first version. It has some known bugs, but can be useful. The second version should be a result of my thesis. I will try to make an english manual soon. Second version will also contain independent reusable VHDL parser (tree & tables).
  • A new version of VHDL SGen will be based on NetBeans RCP.
  • Added VHDL syntax highlighting support for Netbeans IDE (.nbm file in Files). New version of VHDL SGen with VHDL project support is under development.
  • NEW - Check out brand new vhdl tool -> VHDT (VHDL Design Tool) http://sourceforge.net/projects/vhdt

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Additional Project Details

Languages

Czech, English

Intended Audience

Education, Developers, Engineering

User Interface

Java Swing

Programming Language

VHDL/Verilog, Java

Registered

2010-10-21