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EveSoc

alpha
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Description

This project's goal is to provide a simple but extendable SOC (System On Chip) that can be loaded into an FPGA in order to quickly test custom coprocessors and evaluate their robustness against SCA (Side Channel Attacks) or others physical attacks.

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Additional Project Details

Intended Audience

Science/Research

User Interface

Console/Terminal

Programming Language

Python, VHDL/Verilog

Registered

2009-02-18

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