Search Results for "vhdl" - Page 4
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Showing 263 open source projects for "vhdl"
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PHDL
An HDL alternative to PCB graphical schematic capture tools.
PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic... -
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Mojo-VHDL
Mojo FPGA board VHDL projects
Mojo FPGA development board projects in VHDL (starting with the base-project). -
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JavaRock is a project to develop a compiler from java to vhdl, which enables hardware design by java. Developping JavaRock is over, and the project continues in Synthesijer http://synthesijer.sourceforge.net . Like JavaRock, Synthesijer also aims to develop a compiler from Java to VHDL, which enables hardware design by Java. In addition, Synthesijer generates Verilog HDL and aims to implement advanced features such as optimization, graphical tools, and so on.
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Seqview is a tool to document finite state machine (FSM). It reads a VHDL file and generate a diagram. You can edit the diagram to suit your needs. It can generate a postscript file for documenting.
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FPGA starterkit essentials
basic debug tools while using FPGA boards
Module 1: durchblicker: embedded Logicanalyzer with direct output on VGA-monitor -
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cccutils
Clock and Control Card Utilities
cccutils provide the sources of the CCC and the CCC-Fanout. -
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openAut
Open Source Hardware For Industrial Automation
This project is aimed at producing open source hardware for real time use in industrial automation. This project will have a few sub-projects that will focus on individual hardware for various industrial purpose. Some of the sub-projects will be of type Field-IO Modules development, Analog-IO Module development etc. -
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AXI4 BTC Miner
Configurable VHDL bitcoin miner that is AXI4 lite compliant
Configurable FPGA bitcoin miner, from highest performance to the smallest footprint. Easy to implement thanks to its interface AXI4 lite. Generic or vendor specific implementation. Current performance are 300Mhash/s per core on a Xilinx Virtex-7. -
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BlueSVEP
Bluespec SystemVerilog Eclipse Plugin
BlueSVEP is an Eclipse-based IDE for Bluespec SystemVerilog, a functional hardware description language based on a synthesizable subset of Haskell and SystemVerilog. -
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VHDT
VHDL Design Tool - code generation and project management
Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation. -
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"mprfgen" is a multi-port memory generator that can be used for VHDL designs. It can generate either generic or Xilinx-specific (through component instantiation) multi-port memories.
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Oscilloscope components, including 100MHz quad A/D, VHDL code for Xilinx FPGA, and driver for Octave or Matlab.
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Anie
PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e
Embedded system design (VHDL description) based on Xilinx's Spartan3E Development Kit to perform real-time PID control and monitoring of time critical plants such as brushless DC motors, maglevs... vimeo.com/channels/anie prezi.com/gpbycavq499c/anie/ -
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OpenShader
Open architecture GPU simulator and implementation
Documentation, simulator, compiler, and Verilog implementation of a completely open-architecture graphics processing unit. This design is intended for academic and commercial purposes. The first step is to develop a detailed GPU simulator and compiler. The second step is to implement the GPU in synthesizable Verilog. The third step is to develop a feedback loop between the simulator and implementation, allowing power, performance, and reliability aspects of the hardware to feed back into... -
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Minimig is an open source FPGA Amiga chipset re-implementation created and designed by Dennis van Weeren - http://home.hetnet.nl/~weeren001/
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pyCPU
Python Hardware Processor
... into the CPU design. The result can be converted to VHDL or Verilog -
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Sharp MZ800 univerzalni karta periferii 1 ----------------------------------------- Contains peripherals: emulator of FDC WD279x, RTC, single channel SIO, repository manager, LAN10Mbit Chips on the card: STM32F101, XC9356, ENC28J60, FT232RL, MAX3232
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monitoria2011
Descrições de circuitos em VHDL e verilog
Este projeto contem a descrição em VHDL e verilog dos diversos circuitos que implementei durante minha monitoria no IFS que ocorreu no periodo de 2011.2 -
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Application de fines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
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relogio-digital
Relogio digital em VHDL
Este é a descrição de um relogio digital em VHDL para ser implementado em um placa DE2 da terasic e simulado usando o ambiente de desenvolvimento da altera Quartus II. -
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Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.