Search Results for "vhdl"
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Showing 110 open source projects for "vhdl"
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SKUDONET ADC, operates at the application layer, efficiently distributing network load and application load across multiple servers. This not only enhances the performance of your application but also ensures that your web servers can handle more traffic seamlessly.
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ConnectWise CPQ, formerly ConnectWise Sell, is a professional quote and proposal automation software for IT solution providers. ConnectWise CPQ offers a wide range of tools that enables IT solution providers to save time, quote more, and win big. Top features include professional quote or proposal templates, product catalog and sourcing, workflow automation, sales reporting, and integrations with best-in-breed solutions like Cisco, Dell, HP, and Salesforce.
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Free VHDL Parser with Java, Python and T
IEEE VHDL-93 LRM supported parser implemented in Java, APIs Python/Tcl
This parser has been developed for those who wants to develop his/her own tool around VHDL RTL. Only synthesizable subset of VHDL is supported and it may not work for machine/tool generated VHDL files. This parser has been developed in Java in order to make it platform independent. It reads RTL and populates its internal object model. There are APIs to extract the design information from the database, APIs to elaborate the design along with expression evaluation capabilities. This tool has been... -
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GHDL
VHDL 2008/93/87 simulator
This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyze and elaborate sources for generating machine code from your design. Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a code... -
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Clash
Haskell to VHDL/Verilog/SystemVerilog compiler
Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. It provides a familiar structural design approach to both combinational and synchronous sequential circuits. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog. Clash is an open-source project, licensed under the permissive BSD2 license, and actively maintained by QBayLogic. The Clash... -
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Chroma
A general purpose syntax highlighter in pure Go
As Chroma has just been released, its API is still in flux. That said, the high-level interface should not change significantly. Chroma takes source code and other structured text and converts it into syntax-highlighted HTML, ANSI-coloured text, etc. Chroma is based heavily on Pygments and includes translators for Pygments lexers and styles. ABAP, ABNF, ActionScript, ActionScript 3, Ada, Angular2, ANTLR, ApacheConf, APL, AppleScript, Arduino, Awk. PacmanConf, Perl, PHP, PHTML, Pig,... -
Define and Deliver Comprehensive Cybersecurity Services. Security threats continue to grow, and your clients are most likely at risk. Small- to medium-sized businesses (SMBs) are targeted by 64% of all cyberattacks, and 62% of them admit lacking in-house expertise to deal with security issues. Now technology solution providers (TSPs) are a prime target. Enter ConnectWise Cybersecurity Management (formerly ConnectWise Fortify) — the advanced cybersecurity solution you need to deliver the managed detection and response protection your clients require. Whether you’re talking to prospects or clients, we provide you with the right insights and data to support your cybersecurity conversation. From client-facing reports to technical guidance, we reduce the noise by guiding you through what’s really needed to demonstrate the value of enhanced strategy.
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... in the higher leve 5. removehierarchy : Verilog Hierarchy Removal Tool to ungroup all the instances in a given module 6. comparemoduleinterfaces - Diff module ports and parameter. Tool to compare the interfaces ( ports, parameters, SV interfaces ) between two versions of a Verilog module or two similar modules 7. Verilog Testbench Generator 8. VHDL Testbench Generator 9. Verilog Remove Assignments 10. Verilog Find Instances or Nets 11. Clock And Reset Tree Analyzer( Alpha)
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AWS EC2 FPGA
AWS EC2 FPGA hardware and software development Kit
... and can be deployed in a scalable and secure way. Development experience leverages an optimized compiler to allow easy new accelerator development or migration of existing C/C++/openCL, Verilog/VHDL to AWS FPGA instances. Fully custom hardware development experience provides hardware developers with the tools required for developing AFIs for AWS FPGA instances. -
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Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
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wxMEdit
wxMEdit, Cross-platform Text/Hex Editor, Improved Version of MadEdit
•Added automatically checking for updates •Added bookmark support •Added right-click context menu for each tab •Added purging histories support •Added selecting a line by triple click •Added FreeBASIC syntax file •Added an option to place configuration files into %APPDATA% directory under Windows •Improved support for Find/Replace •Improved Mac OS X support •Improved system integration under Windows •Improved encoding detection result •Improved Hex editing support •Added more... -
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UMHDL
Integrated Development Environment (IDE) for learning HDL
UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So... -
With the world of work changed forever, it’s essential to manage your workplace and assets together to effectively create a high-performing environment. The Eptura experience combines the power of workplace management software with asset management, enabling you to effectively operate your building and facilitate hybrid work.
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MSX++ Official Firmware for the following machines. 1st Gen => 1chipMSX, Zemmix Neo (KR), Zemmix Neo BR, SX-1 and SX-1 Mini/Mini+. 2nd Gen => SM-X and SX-2.
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EDAUtils Converters
Free converters across IP-XACT Verilog VHDL Liberty SystemC
verilog2vhdl : Tool to convert Verilog into VHDL by keeping the same structure and function for ease of correlation. vhdl2verilog : Tool to convert VHDL into Verilog by keeping the same structure and function for ease of correlation verilog2ipxact :Tool to create IP-XACT Component or Design from a Verilog Module. ipxact2verilog : Tool to convert IP-XACT into Verilog module ipxactinterface2svinterface : Converts IP-XACT Bus Definition / BusInterface into System Verilog Interface... -
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A new 64-bit RISC platform, complemented by a set of development tools, standards specifications and synthesizable VHDL implementations.
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myScite
The allRound pocket sized CodeEditor.
Refurbished Scintilla.orgs/SciTE with some additional patches. -- Features -- - Full MinGW and GTK SDKs Autocomplete.(190+) - Do system scripting (bash, applescript, cmd, powershell, perl, j/vbscript, awk) - Examine all sorts of data files (sql, regedit, mib, xml, yaml, json, vcard ...) - Review difference and patch files - Create makefiles (gnu make / cmake) - Edit html, css and config files (with calltips) - Describe circuits in vhdl and spice. ... - And finally; read & write... -
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StateS
Draw and Simulate Finite States Machines (FSM)
Simple tool for drawing Finite State Machines (FSMs). StateS has moved to GitHub and will no longer be updated on SourceForge. New link: https://github.com/ClementFoucher/StateS -
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Controlix
An operating system written in RTL
Controlix is a virtual-circuit based operating system written in RTL. -
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vrq is verilog parser that supports plugin tools to process verilog. Current plugins include tools to perform x-propagation and to auto build hiearchy.
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XBioSiP
RTL & Behavioral Models (Approx.) of Pan-Tompkins Application Stages
The "XBioSiP" library contains the RTL (VHDL) and behavioral (MATLAB) models of the approximate adders and multipliers used for designing approximate versions of the bio-signal processing Pan-Tompkins algorithm, including all of its application stages. This work was published in DAC 2019. In case of usage please refer to: B. S. Prabakaran, S. Rehman, M. Shafique, “XBioSiP: A Methodology for Approximate Bio-Signal Processing at the Edge”, IEEE/ACM 56th Design Automation Conference (DAC... -
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Please, get the last version from http://sba.accesus.com/software-tools/sba-creator
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Wheefun Computer Prototyping Kit
A Toolkit for Designing Computers
This package is designed for people who are a) interested in writing emulators or b) integrating this level of detain into their applications (e.g., a video game). The ability to do this is useful because a) it allows for tinkering far before physical implementation of the design is. In addition to a strong core, WFCPK will also include modules emulating various processors (e.g., the MOS 6502 and the Zilog Z80) as well as the Video-Audio Interface (a custom VGA-compatible display and... -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
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ApproxFPGAs
An Open-source Approximate Adder Library for FPGAs
The "ApproxFPGAs" library contains all the RTL (VHDL) and behavioral (MATLAB) models of FPGA-based approximate adder designs presented at DATE 2018. In case of usage please refer to: B. S. Prabakaran, S. Rehman, M. A. Hanif, S. Ullah, G. Mazaheri, A. Kumar, M. Shafique, “DeMAS: An Efficient Design Methodology for Building Approximate Adders for FPGA-Based Systems”, IEEE/ACM 21st Design, Automation and Test in Europe Conference (DATE), March, 2018. -
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Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.
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zamiaCAD is a modular and extensible platform for HW design, analysis, and research. It translates a HW description (VHDL or Verilog) into a language independent IG structure. Applications like a simulator and an eclipse GUI build on top of the IG.