Search Results for "vhdl"
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Showing 71 open source projects for "vhdl"
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AWS EC2 FPGA
AWS EC2 FPGA hardware and software development Kit
... and can be deployed in a scalable and secure way. Development experience leverages an optimized compiler to allow easy new accelerator development or migration of existing C/C++/openCL, Verilog/VHDL to AWS FPGA instances. Fully custom hardware development experience provides hardware developers with the tools required for developing AFIs for AWS FPGA instances. -
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A new 64-bit RISC platform, complemented by a set of development tools, standards specifications and synthesizable VHDL implementations.
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pyrpl
PyRPL turns your Red Pitaya into a powerful analog feedback device.
The Red Pitaya is a commercial, affordable FPGA board with fast analog inputs and outputs. This makes it useful for quantum optics experiments, in particular as a digital feedback controller for analog systems. Based on the open source software provided by the board manufacturer, PyRPL (Python RedPitaya Lockbox) implements many devices that are needed for optics experiments with the Red Pitaya. PyRPL implements various digital signal processing (DSP) modules (see features below). It allows... -
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Controlix
An operating system written in RTL
Controlix is a virtual-circuit based operating system written in RTL. -
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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32-BIT GENERAL PURPOSE INTEGER PROCESSOR
Simple single cycle processor based on triadic Harvard architecture.
A 32-bit MIPS simple single cycle processor based on triadic Harvard architecture with a RISC-like ISA. This project is done in Cairo University-Faculty of Enigneering, Electronics and Electrical Communication department (EECE-2017) -
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lpACLib
An Open-Source Library for Low-Power Approximate Computing Modules
The “lpACLib” library contains the VHDL description of accurate and approximate versions of several arithmetic modules (like adders and multiplier of different bit-widths) and accelerators. Moreover, it also provides the corresponding software behavioral models/implementations developed in C and MATLAB to enable quality characterization. Besides our novel designs, it also contains implementations for several state-of-the-art arithmetic modules and their approximate versions. This open-source... -
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COFILOS
A Development Framework for Coldfire
Contains a framework for Coldfire MCUs like 52254. The framework supports a Command Line Interface (CLI) that may work from Serial port, USB or ENET. The framework uses Processor Expert and IDE requirement is MCU Eclipse 10.4 from Freescale. Includes the FunkOS Realtime Operating System by Funkenstein Software Consulting, available at http://funkos.sourceforge.net Mainly it is a support package for the development board Perseus, but I have ported also the RTOS to MCF52233DEMO... -
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ApproxAdderLib
Library of Approximate Adders
We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as... -
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MatlabSimulink2CPP
Demo of Simulink to C++ C or HDL FGA for HFT potential
Video and files download for Visual trading idea to C++ or FPGA HFT Meetup File download sample: test model (Matlab 2014b with Visual Studio 2013 C++ project generated) Powerpoint MATLAB SIMULINK http://quantlabs.net/blog/2015/04/video-and-files-download-for-visual-trading-idea-to-c-or-fpga-hft-meetup/ -
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cMIPS
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips The code here is no longer up to date. The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5% logic... -
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EduCPU
Simple CPU for education
This is a simple CPU design, written in Verilog, intended for educational purposes. The objective is to provide a simulatable processor where the source code exposes concepts in CPU microarchitecture. -
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OpenSOC86
Open implementation of the x86 architecture
OpenSOC86 is an open implementation of the x86 architecture in Verilog. The current version only implements the 16-bit part (real mode). The processor is a pipelined architecture clocked at 100 MHz in a Cyclone II speed grade -6. Therefore it can be seen as similar to a 486 in real mode. Several peripherals are also implemented in a somewhat minimalistic way, but enough to be able to boot an IBM PCXT compatible bios and MSDOS 6.22. The current implementation is only proven to boot the... -
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openAut
Open Source Hardware For Industrial Automation
This project is aimed at producing open source hardware for real time use in industrial automation. This project will have a few sub-projects that will focus on individual hardware for various industrial purpose. Some of the sub-projects will be of type Field-IO Modules development, Analog-IO Module development etc. -
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OpenShader
Open architecture GPU simulator and implementation
Documentation, simulator, compiler, and Verilog implementation of a completely open-architecture graphics processing unit. This design is intended for academic and commercial purposes. The first step is to develop a detailed GPU simulator and compiler. The second step is to implement the GPU in synthesizable Verilog. The third step is to develop a feedback loop between the simulator and implementation, allowing power, performance, and reliability aspects of the hardware to feed back into... -
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pyCPU
Python Hardware Processor
... into the CPU design. The result can be converted to VHDL or Verilog -
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Sharp MZ800 univerzalni karta periferii 1 ----------------------------------------- Contains peripherals: emulator of FDC WD279x, RTC, single channel SIO, repository manager, LAN10Mbit Chips on the card: STM32F101, XC9356, ENC28J60, FT232RL, MAX3232
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Partially Reconfigurable Hardware
Framework for Adaptive Hardware Concurrent Systems with DPR-FPGAs
This project introduces new FPGA architectural tools and Linux OS modifications that aid in supporting Dynamic Partial Reconfiguration (DPR) on FPGAs for concurrent control. It shows that control systems benefit from hardware concurrency, meaning that by moving the control intelligence into hardware, the negative effects inherent to threads and their scheduler are minimized. This leaves software with the role of a high-level administrator rather than an executor, thereby eliminating... -
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FPGAsm
Create fast bare-metal FPGA designs without Verilog or VHDL
FPGAsm is a low-level alternative to verilog and VHDL. A near-instant 'assembler for FPGAs', this simple yet powerful language facilitates bottom-up design, layout and wiring of modules, and generation of .xdl output. With about 10 keywords to learn, you can start making circuits in minutes. Now you can focus on learning the ins and outs of the FPGA instead of complex tools and languages. Fast turnaround time and bottom-up approach invite exploration, experimentation, live circuit... -
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ASDM-NoC
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
This project provide a reconfigurable asynchronous SDM router which can be configured into a basic wormhole router or an SDM router with multiple virtual circuits in every direction. Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation *... -
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FAZIA DAQ
The aim of FAZIA project is to build a 4Pi array for charged particles
The FAZIA project groups together more than 10 institutions in Nuclear Physics, which are working in the domain of heavy-ion induced reactions around and below the Fermi energy (10-100AMeV). The aim of the project is to build a 4Pi array for charged particles, with high granularity and good energy resolution, with A and Z identification capability over the widest possible range. It will use the up-to-date techniques concerning detection, signal processing and data flow, with full digital... -
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AVRILOS
Simple AVR OS
A simple Embedded System Framework that allows rapid development of applications build for AVR family. System is based on a super-loop architecture with check and skip (no-wait) flag event driver system. Supports: UART, SysTick Timer, ADC, SPI, EEPROM, PWM. Also supports: Xilinx FPGA configuration, FPGA SSI interface, smart card reader etc. Tested partially (different modules in each case) on ATMega163/16/32/323/8. Awards CodeProject 2010, Third Prize, Hardware and Device... -
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Este proyecto presenta GraphUIS, una implementación de un periférico de video en un FPGA como un diseño modular caracterizado por no tener memoria dedicada. Se desarrolló como un proyecto académico en la Universidad Industrial de Santander.