SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

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Categories

Text Processing, Hardware, Electronic Design Automation (EDA)

License

GNU Library or Lesser General Public License version 3.0 (LGPLv3)

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Additional Project Details

Operating Systems

BSD, Cygwin, Linux, MinGW/MSYS2

Intended Audience

Developers, Engineering, Science/Research

User Interface

Command-line

Programming Language

Perl, VHDL/Verilog

Related Categories

Perl Text Processing Software, Perl Hardware Platform, Perl Electronic Design Automation (EDA) Software, VHDL/Verilog Text Processing Software, VHDL/Verilog Hardware Platform, VHDL/Verilog Electronic Design Automation (EDA) Software

Registered

2010-06-11
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