Search Results for "vhdl"
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Showing 15 open source projects for "vhdl"
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We design our technology to make workforce management easier. APS offers core HR, payroll, benefits administration, attendance, recruiting, employee onboarding, and more.
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When it comes to cybersecurity, what your clients don’t know can really hurt them. And believe it or not, keep them safe starts with asking questions. With ConnectWise Identify Assessment, get access to risk assessment backed by the NIST Cybersecurity Framework to uncover risks across your client’s entire business, not just their networks. With a clearly defined, easy-to-read risk report in hand, you can start having meaningful security conversations that can get you on the path of keeping your clients protected from every angle. Choose from two assessment levels to cover every client’s need, from the Essentials to cover the basics to our Comprehensive Assessment to dive deeper to uncover additional risks. Our intuitive heat map shows you your client’s overall risk level and priority to address risks based on probability and financial impact. Each report includes remediation recommendations to help you create a revenue-generating action plan.
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IP-XACT 2009/2014 Platform
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API support... -
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myScite
The allRound pocket sized CodeEditor.
Refurbished Scintilla.orgs/SciTE with some additional patches. -- Features -- - Full MinGW and GTK SDKs Autocomplete.(190+) - Do system scripting (bash, applescript, cmd, powershell, perl, j/vbscript, awk) - Examine all sorts of data files (sql, regedit, mib, xml, yaml, json, vcard ...) - Review difference and patch files - Create makefiles (gnu make / cmake) - Edit html, css and config files (with calltips) - Describe circuits in vhdl and spice. ... - And finally; read & write... -
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Baya - SoC Integration Platform
Best in class SoC Integration Platform, IP-XACT, Verilog VHDL, UPF
1. Comes with 200+ high level Tcl commands around SoC platform assembly 2. Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya 3. Adhoc and Interface based connections 4. Autoconnections 5. Rule based connections between component ports 6. A variety of SoC integration Methodologies 6.a. XLS/CSV Based connections 6.b. Port-to-Port Adhoc connections 6.c. IP-XACT and System Verilog Interface based connections 6.d. ... 7. Maintains a connectivity... -
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pyrpl
PyRPL turns your Red Pitaya into a powerful analog feedback device.
The Red Pitaya is a commercial, affordable FPGA board with fast analog inputs and outputs. This makes it useful for quantum optics experiments, in particular as a digital feedback controller for analog systems. Based on the open source software provided by the board manufacturer, PyRPL (Python RedPitaya Lockbox) implements many devices that are needed for optics experiments with the Red Pitaya. PyRPL implements various digital signal processing (DSP) modules (see features below). It allows... -
ConnectWise CPQ, formerly ConnectWise Sell, is a professional quote and proposal automation software for IT solution providers. ConnectWise CPQ offers a wide range of tools that enables IT solution providers to save time, quote more, and win big. Top features include professional quote or proposal templates, product catalog and sourcing, workflow automation, sales reporting, and integrations with best-in-breed solutions like Cisco, Dell, HP, and Salesforce.
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HDL Checker
Repurposing existing HDL tools to help writing better code
HDL Checker is a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up. It supports Language Server Protocol or a custom HTTP interface; can infer the library VHDL files likely to belong to, besides working out mixed language dependencies, compilation order, interpreting some compiler messages and providing some (limited) static checks. Notice that currently, the unused reports has caveats, namely declarations with the same... -
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COFILOS
A Development Framework for Coldfire
Contains a framework for Coldfire MCUs like 52254. The framework supports a Command Line Interface (CLI) that may work from Serial port, USB or ENET. The framework uses Processor Expert and IDE requirement is MCU Eclipse 10.4 from Freescale. Includes the FunkOS Realtime Operating System by Funkenstein Software Consulting, available at http://funkos.sourceforge.net Mainly it is a support package for the development board Perseus, but I have ported also the RTOS to MCF52233DEMO... -
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A programmable signal generator and RF synthesizer for scientific experiments, especially quantum computing and quantum information processing. It includes hardware, firmware, software, and documentation, all under an open source license.
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pyCPU
Python Hardware Processor
... into the CPU design. The result can be converted to VHDL or Verilog -
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This project includes a set of tools and guidelines designed for rapid production of large-scale embedded systems projects. The tools enable quick generation of reusable, reconfigurable hardware, using a user-specified hardware description language.
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Chat with your business data with Looker. More than just a modern business intelligence platform, you can turn to Looker for self-service or governed BI, build your own custom applications with trusted metrics, or even bring Looker modeling to your existing BI environment.
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This project's goal is to provide a simple but extendable SOC (System On Chip) that can be loaded into an FPGA in order to quickly test custom coprocessors and evaluate their robustness against SCA (Side Channel Attacks) or others physical attacks.
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Synthesia is an open hardware/software platform intended for creating standalone audio devices such as synthesizers on embedded processors.
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The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.
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Labcoat: Cleanroom Apps for SuperWikia
Labcoat; the VHDL graphic emulator.
Labcoat for SuperWikia Alpha fabrication manages new or revised fabrication processes. Its 'Cleanroom' applets allow codesmiths to access the lab environment, used to create semiconductors, substrate prototypes, chipset instruction blocks and other Labcoat projects. Our extensions in future releases will include UML support for C#/C++ conforming projects, import/export architecture schematics and refactoring sub-projects.
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