1. Comes with 200+ high level Tcl commands around SoC platform assembly
2. Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya
3. Adhoc and Interface based connections
4. Autoconnections
5. Rule based connections between component ports
6. A variety of SoC integration Methodologies
6.a. XLS/CSV Based connections
6.b. Port-to-Port Adhoc connections
6.c. IP-XACT and System Verilog Interface based connections
6.d. ...
7. Maintains a connectivity database with advance queries
8. Hierarchy Manipulation to create Power Domain, Voltage Domain, comply with Floor planning
8.a. Insert new hierarchy
8.b. Remove existing hierarchy
9. Associate the IP-XACT memory maps with the SoC component instances
10. Dump out the C Model for the entire design
11. Glue-Logic insertion
12. Spare port insertion across hierarchies
13. Automatic creation of the top module and it's ports based upon specified rule
14. Creates stub module

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Additional Project Details

Operating Systems

Linux, Windows

Programming Language

Java, Python, Tcl

Related Categories

Python Electronic Design Automation (EDA) Software, Tcl Electronic Design Automation (EDA) Software, Java Electronic Design Automation (EDA) Software

Registered

2024-01-20