IEEE VHDL-93 LRM supported parser implemented in Java, APIs Python/Tcl
VHDL 2008/93/87 simulator
Integrated Development Environment (IDE) for learning HDL
Schematic circuit editor for VLSI and Mixed mode circuit simulation.
Free converters across IP-XACT Verilog VHDL Liberty SystemC
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
Open hardware SPM controller with advanced sampling support.
Best in class SoC Integration Platform, IP-XACT, Verilog VHDL, UPF
Draw and Simulate Finite States Machines (FSM)
PyRPL turns your Red Pitaya into a powerful analog feedback device.
my personal verilog code collection
Tools and libraries for use with systemc and verilog
Verilog Finite State Machine (FSM) Code Generator
Programmable Electronic Controller
FFT co-processor in Verilog based on the KISS FFT
GPS to Radio-controlled Clock