Search Results for "vhdl"
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Showing 48 open source projects for "vhdl"
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Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
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wxMEdit
wxMEdit, Cross-platform Text/Hex Editor, Improved Version of MadEdit
•Added automatically checking for updates •Added bookmark support •Added right-click context menu for each tab •Added purging histories support •Added selecting a line by triple click •Added FreeBASIC syntax file •Added an option to place configuration files into %APPDATA% directory under Windows •Improved support for Find/Replace •Improved Mac OS X support •Improved system integration under Windows •Improved encoding detection result •Improved Hex editing support •Added more... -
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A new 64-bit RISC platform, complemented by a set of development tools, standards specifications and synthesizable VHDL implementations.
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myScite
The allRound pocket sized CodeEditor.
Refurbished Scintilla.orgs/SciTE with some additional patches. -- Features -- - Full MinGW and GTK SDKs Autocomplete.(190+) - Do system scripting (bash, applescript, cmd, powershell, perl, j/vbscript, awk) - Examine all sorts of data files (sql, regedit, mib, xml, yaml, json, vcard ...) - Review difference and patch files - Create makefiles (gnu make / cmake) - Edit html, css and config files (with calltips) - Describe circuits in vhdl and spice. ... - And finally; read & write... -
Our robust pre-built connectors and our no-code, drag-and-drop interface makes it easy and fast to automatically sync vendors, invoices, and invoice payment data between Tipalti and your ERP or accounting software.
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StateS
Draw and Simulate Finite States Machines (FSM)
Simple tool for drawing Finite State Machines (FSMs). StateS has moved to GitHub and will no longer be updated on SourceForge. New link: https://github.com/ClementFoucher/StateS -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.
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ipdbg
IPDBG are free tools to debug intellectual properties (IP cores).
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BrightGauge, a ConnectWise solution, was started in 2011 to fill a missing need in the small-to-medium IT Services industry: a better way to manage data and provide the value of work to clients. BrightGauge Software allows you to display all of your important business metrics in one place through the use of gauges, dashboards, and client reports. Used by more than 1,800 companies worldwide, BrightGauge integrates with popular business solutions on the market, like ConnectWise, Continuum, Webroot, QuickBooks, Datto, IT Glue, Zendesk, Harvest, Smileback, and so many more. Dig deeper into your data by adding, subtracting, multiplying, and dividing one metric against another. BrightGauge automatically computes these formulas for you. Want to show your prospects how quick you are to respond to tickets? Show off your data with embeddable gauges on public sites.
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Project 2306 IDE Rad MacOS MCU DeveR
Electronic design and programming tools suite like Eagle, MpLab
Currently Only MacOS is Present, PreAlpha means not Ready to use, Application is provided Without Strict Garantee, License not OSI. All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned... -
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Notepad3
Light-weight Scintilla-based text editor with syntax highlighting
Notepad3 is a fast and light-weight Scintilla-based text editor with syntax highlighting. Notepad3 is an excellent replacement for the default Windows text editor. Notepad3 offers many extra features over Notepad. It has a small memory footprint, but is powerful enough to handle most programming jobs. -
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PLP
Powerfull pre-processor
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc) -
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CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
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Caneda
Caneda (Circuits and Networks EDA) is an open source EDA software.
Caneda (Circuits and Networks EDA) is an open source EDA software focused on easy of use and portability. While in the short term schematic capture and simulation is the primary goal, in the long term future, PCB and layout edition will be covered. -
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
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MatlabSimulink2CPP
Demo of Simulink to C++ C or HDL FGA for HFT potential
Video and files download for Visual trading idea to C++ or FPGA HFT Meetup File download sample: test model (Matlab 2014b with Visual Studio 2013 C++ project generated) Powerpoint MATLAB SIMULINK http://quantlabs.net/blog/2015/04/video-and-files-download-for-visual-trading-idea-to-c-or-fpga-hft-meetup/ -
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NOCEXplore
Network-on-Chip design exploration tool based on SystemC.
NOCEXplore is a Network-on-Chip design exploration tool based on SystemC. It includes libraries and executables for easy and fast upgradeable NoC models and a set of shell scripts. The project started during the PhD of Stefano Gigli at DII of Universita' Politecnica delle Marche (http://www.dii.univpm.it/) under the supervision of Prof. Massimo Conti and contribution of several students. -
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OpenShader
Open architecture GPU simulator and implementation
Documentation, simulator, compiler, and Verilog implementation of a completely open-architecture graphics processing unit. This design is intended for academic and commercial purposes. The first step is to develop a detailed GPU simulator and compiler. The second step is to implement the GPU in synthesizable Verilog. The third step is to develop a feedback loop between the simulator and implementation, allowing power, performance, and reliability aspects of the hardware to feed back into... -
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Minimig is an open source FPGA Amiga chipset re-implementation created and designed by Dennis van Weeren - http://home.hetnet.nl/~weeren001/
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HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL
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FPGAsm
Create fast bare-metal FPGA designs without Verilog or VHDL
FPGAsm is a low-level alternative to verilog and VHDL. A near-instant 'assembler for FPGAs', this simple yet powerful language facilitates bottom-up design, layout and wiring of modules, and generation of .xdl output. With about 10 keywords to learn, you can start making circuits in minutes. Now you can focus on learning the ins and outs of the FPGA instead of complex tools and languages. Fast turnaround time and bottom-up approach invite exploration, experimentation, live circuit... -
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Its a VHDL plugin for Notepad++ which is simular with the one which is available on emacs (Copy a selcted entity port and then paste it as instatiation , Signals or as Testbench )
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FAZIA DAQ
The aim of FAZIA project is to build a 4Pi array for charged particles
The FAZIA project groups together more than 10 institutions in Nuclear Physics, which are working in the domain of heavy-ion induced reactions around and below the Fermi energy (10-100AMeV). The aim of the project is to build a 4Pi array for charged particles, with high granularity and good energy resolution, with A and Z identification capability over the widest possible range. It will use the up-to-date techniques concerning detection, signal processing and data flow, with full digital...