HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL

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User Reviews

  • sim-sim is perfect tool for synthesis, although I have noticed some problems with output formatting, netlist optimalization and absence of documentation.

  • This is AWESOME indeed. But it is hard to find and it really could use some documentation...

  • Sim-sim works excellent.

    1 user found this review helpful.
  • This project is AWESOME! Please present it more prominently so others can find it easier. At first I didn't try it because there was so little information here..

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Additional Project Details

User Interface

Qt

Programming Language

Perl, C++, VHDL/Verilog, Yacc

Registered

2006-07-12