Search Results for "java open source"
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Showing 31 open source projects for "java open source"
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Atera all-in-one platform IT management software with AI agentsAtera’s AI agents don’t just assist, they act. From detection to resolution, they handle incidents and requests instantly, taking your IT management from automated to autonomous.
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Free and Open Source HR SoftwareGive your HR team the tools they need to streamline administrative tasks, support employees, and make informed decisions with the OrangeHRM free and open source HR software.
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GHDL
VHDL 2008/93/87 simulator
This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyze and elaborate sources for generating machine code from your design. Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. ... -
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AWS EC2 FPGA
AWS EC2 FPGA hardware and software development Kit
AWS EC2 FPGA Development Kit is a set of development and runtime tools to develop, simulate, debug, compile and run hardware-accelerated applications on Amazon EC2 F1 instances. It is distributed between this GitHub repository and FPGA Developer AMI - Centos/AL2 provided by AWS with no cost of development tools. After creating an FPGA design (also called CL - Custom logic), developers can create an Amazon FPGA Image (AFI) and easily deploy it to an F1 instance. AFIs are reusable, shareable... -
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Wheefun Computer Prototyping Kit
A Toolkit for Designing Computers
This package is designed for people who are a) interested in writing emulators or b) integrating this level of detain into their applications (e.g., a video game). The ability to do this is useful because a) it allows for tinkering far before physical implementation of the design is. In addition to a strong core, WFCPK will also include modules emulating various processors (e.g., the MOS 6502 and the Zilog Z80) as well as the Video-Audio Interface (a custom VGA-compatible display and... -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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Desktop and Mobile Device Management SoftwareDesktop Central is a unified endpoint management (UEM) solution that helps in managing servers, laptops, desktops, smartphones, and tablets from a central location.
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ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
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PLP
Powerfull pre-processor
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc) -
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CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
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FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
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ApproxAdderLib
Library of Approximate Adders
...These MATALB and Verilog models can allow software programmer as well as hardware designers to evaluate their code and design. To the best of our knowledge, this is the first open-source library of approximate adders that facilitates reproducible comparisons and further research and development in this direction across various layers of design abstraction. This work is a result of collaborative effort between Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany and Vision Image and Signal Processing (VISpro) Lab at SEECS-NUST, Pakistan. -
FDM4: Cloud-Based Enterprise Resource Planning SolutionsFDM4 is the best solution for ERP software tailored for the apparel industry. The best way to know a company, take a look inside. Our corporate video takes you through the FDM4 International office, introducing our team and our values as a corporation. We offer a solution that ties together software, hardware, development, and design to provide you with the answer to your business needs. Learn more about FDM4 and our dedication to growing your business. The most difficult part of choosing a software solution? Finding a solution that both meets your needs, and complies with the industry’s standards. At FDM4 we’ve thought of that, which is why we have built our software to be multi-purposed and multi-functioning. To meet your needs, whether apparel, hard goods, or consumer goods, no matter what those needs may be. Nothing tells you more about a company than the clients. Which is why we invite you to explore the clients that have grown with FDM4.
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Notepad++ Verilog Plugin
Verilog plugin for Notepad++
Verilog processor for Notepad++. Current features: - Instantiate a module - Insert registers/wires from a module - Generate a test bench template - Automatically inserts a default header for a test bench - Insert a clocked always block v1.2.0 now supports ANSI and non-ANSI module declarations. To use this plugin, select the module declaration (including parameter and I/O definitions below for non-ANSI) and click SHIFT-CTRL-C. This selects the module and parses its components.... -
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VHDT
VHDL Design Tool - code generation and project management
Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation. -
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This is a collection of tools and a code library to assist engineers who are developing SystemVerilog based verification environments. Components include utility libraries, scoreboard and shutdown manager implementation, register tool, etc.
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Application de fines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
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AVRILOS
Simple AVR OS
A simple Embedded System Framework that allows rapid development of applications build for AVR family. System is based on a super-loop architecture with check and skip (no-wait) flag event driver system. Supports: UART, SysTick Timer, ADC, SPI, EEPROM, PWM. Also supports: Xilinx FPGA configuration, FPGA SSI interface, smart card reader etc. Tested partially (different modules in each case) on ATMega163/16/32/323/8. Awards CodeProject 2010, Third Prize, Hardware and Device... -
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vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.
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Writing Testbenches for FPGA/ASIC design is always a very fastidious and boring task. This project helps any FPGA/ASIC designer by providing a full RTL test environment with C support.
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The project goal is to develop several IP cores that would implement artificial neural networks using FPGA resources. These cores will be designed in such a way to allow easy integration in the Xilinx EDK framework.
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Synthesia is an open hardware/software platform intended for creating standalone audio devices such as synthesizers on embedded processors.
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This is an image coder with fixed sampling, at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with res. up to 352x288).
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Compiler-like program that checks Verilog source for common design errors. This tool can help beginning Verilog programmers who aren't aware of common design pitfalls and advanced Verilog programmers who want to double check large projects.
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the goal of this project is to build a stack for Lonworks Protocol and device working on this protocol
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This project aims to develop a colour-based vision processing system for use in RoboCup. We are using a CCD camera for input to an FPGA. The system locates coloured objects and outputs detected corners.
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Plugin Eclipse/VDT supports hardware development in VHDL/Verilog, allowing to easily integrate command-line controlled tools in Eclipse. Underlying Eclipse/ExDT plugin provides integration means that may be used for other languages and applications.
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Software to support the JTAG bus (IEEE 1149.1). Primary purpose is for a JTAG programmer/debugger using FPGA's to provide ability to test and program JTAG devices.
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The OS561 operating system based around FORTH/Java. The OS is to run on a VHDL chip OpenHardware design called the Minon, but could become available for other platforms. The unique point of the design is a revolutionary data compression technology.
