This is a collection of tools and a code library to assist engineers who are developing SystemVerilog based verification environments. Components include utility libraries, scoreboard and shutdown manager implementation, register tool, etc.

Project Activity

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Categories

UML, Frameworks, Object Oriented, Electronic Design Automation (EDA), Libraries, Admin Templates

License

Apache License V2.0

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Additional Project Details

Operating Systems

Linux, Windows

Intended Audience

Advanced End Users, Developers, Education, Science/Research, Telecommunications Industry

Programming Language

C++, VHDL/Verilog

Related Categories

C++ UML Tool, C++ Frameworks, C++ Object Oriented Software, C++ Electronic Design Automation (EDA) Software, C++ Libraries, VHDL/Verilog UML Tool, VHDL/Verilog Frameworks, VHDL/Verilog Object Oriented Software, VHDL/Verilog Electronic Design Automation (EDA) Software, VHDL/Verilog Libraries

Registered

2009-05-16
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