Compiler-like program that checks Verilog source for common design errors. This tool can help beginning Verilog programmers who aren't aware of common design pitfalls and advanced Verilog programmers who want to double check large projects.

Project Samples

Well, it's a command line tool; what did you expect?

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Categories

Design

License

BSD License

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Additional Project Details

Intended Audience

Developers, Science/Research

Programming Language

C++, VHDL/Verilog

Related Categories

C++ Design Software, VHDL/Verilog Design Software

Registered

2007-03-28
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