Verilog Design Checker / News: Recent posts

Now that we handed in this project for a grade, it's time for a major rewrite. I'm in the process of rewriting the parser, from scratch, based on the 2005 Verilog specification. This alone will probably take two weeks, not to mention debugging and putting the old functionality back in.

By the time the overhaul is complete (hopefully around September 2007), there should be many new fancy features, like checking for race conditions and implicit latches.... read more