Search Results for "verilog code ofdm"
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28 programs for "verilog code ofdm" with 1 filter applied:
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wxMEdit
wxMEdit, Cross-platform Text/Hex Editor, Improved Version of MadEdit
... choices for data format copying/pasting in Hex Area •Added new feature: Paste with Overwriting in Hex Area •Improved encoding support --Added grouping of encodings --Added new encodings: ISO-8859-16,CP1258,KOI8-R/U,GB18030,CP850,CP852,CP855,CP866,CP437 for ASCII-Art •Redesigned dialogs with Code::Blocks wxSmith •Updated translations --Added Spanish,Russian,German,Polish translation --Updated Chinese and Japanese translations •Other fixes and changes -
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ALCHA
A New Programming Language for FPGA Projects
ALCHA aims to reduce FPGA project develop time by means of automation and abstraction, but without loosing the low-level control that HDLs, such as Verilog, provides. It will support an object oriented programming model, abstract data and signal types, and compile-time scripting. -
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
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DRAKON Editor
A free cross-platform editor for the DRAKON visual language.
DRAKON is a diagram language developed within the Russian space program. Its primary objective is presenting complex software systems in a way which is easy to understand by humans. DRAKON's motto: took a glance - understood at once. DRAKON Editor helps software architects, quality specialists and developers. Architects and quality assurers can express a high-level view of how their product works. DRAKON serves them to explain the dynamics of a software system. Software engineers can use... -
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ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
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Project 2306 IDE Rad MacOS MCU DeveR
Electronic design and programming tools suite like Eagle, MpLab
Currently Only MacOS is Present, PreAlpha means not Ready to use, Application is provided Without Strict Garantee, License not OSI. All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned... -
Test your software product anywhere in the worldGlobal App Testing is a managed pool of freelancers used by Google, Meta, Microsoft, and other world-beating software companies.
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PLP
Powerfull pre-processor
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc) -
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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ApproxAdderLib
Library of Approximate Adders
We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well... -
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Oscilloscope components, including 100MHz quad A/D, VHDL code for Xilinx FPGA, and driver for Octave or Matlab.
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VHDT
VHDL Design Tool - code generation and project management
Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation. -
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Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.
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VPreproc
C++ Verilog macro preprocessor
This is a standalone preprocessor for the Verilog HDL language. It is modified from the Verilog-PreProcessor of Verilog Perl tool 3.314. Most of the code is written by the team led by Wilson Snyder. What I have done in this project: * Provide a standalone command line interface (without Perl). * Replace the parts implemented in Perl to C++. * Encapsulate the package in a separated namespace for better independence. What I may do in the future: * Replace the C language features to C... -
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Application de fines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
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Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered
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vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.
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OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.
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Custom Architecture Generator Tool is a software based on the Netbeans Platform, the main purpose is to accelerate the embedded system realisation with a high level description: VHDL code,C2VHDL conversion,Quartus project generation,real time application
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The Affordable BIOS Restoration Tool provides VHDL and C code to recover from failed BIOS upgrades using affordable CPLD's. EEPROM's and Flash chips can be restored with this flash programmer. Interfaces for DIP and tsop packages are being developed.
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RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.
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Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
