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Showing 70 open source projects for "verilog code ofdm"
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Sloc Cloc and Code (scc)
Sloc, Cloc and Code: scc is a very fast accurate code counter
Sloc, Cloc and Code: scc is a very fast accurate code counter with complexity calculations and COCOMO estimates written in pure Go. The tool is similar to cloc, sloccount and tokei. For counting the lines of code, blank lines, comment lines, and physical lines of source code in many programming languages. The goal is to be the fastest code counter possible, but also perform COCOMO calculations like sloccount, estimate code complexity similar to cyclomatic complexity calculators, and produce... -
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GHDL
VHDL 2008/93/87 simulator
This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyze and elaborate sources for generating machine code from your design. Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a code... -
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Clash
Haskell to VHDL/Verilog/SystemVerilog compiler
... project is a Haskell Foundation affiliated project. Clash is built on Haskell which provides an excellent foundation for well-typed code. Together with Clash's standard library it is easy to build scalable and reusable hardware designs. Load your designs in an interpreter and easily test all your component without needing to setup a test bench. Although Clash offers many features, you sometimes need to directly access VHDL, Verilog, or SystemVerilog directly. -
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Chroma
A general purpose syntax highlighter in pure Go
As Chroma has just been released, its API is still in flux. That said, the high-level interface should not change significantly. Chroma takes source code and other structured text and converts it into syntax-highlighted HTML, ANSI-coloured text, etc. Chroma is based heavily on Pygments and includes translators for Pygments lexers and styles. ABAP, ABNF, ActionScript, ActionScript 3, Ada, Angular2, ANTLR, ApacheConf, APL, AppleScript, Arduino, Awk. PacmanConf, Perl, PHP, PHTML, Pig, PkgConfig... -
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System Verilog Parser IEEE 1800 LRM
IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API
This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities. It has been bundled as an executable JAR file along with a sample application which reads a RTL file(s), elaborates and dumps it back to show the users... -
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Official firmware for MSX++ computers and compatibles.
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wxMEdit
wxMEdit, Cross-platform Text/Hex Editor, Improved Version of MadEdit
... choices for data format copying/pasting in Hex Area •Added new feature: Paste with Overwriting in Hex Area •Improved encoding support --Added grouping of encodings --Added new encodings: ISO-8859-16,CP1258,KOI8-R/U,GB18030,CP850,CP852,CP855,CP866,CP437 for ASCII-Art •Redesigned dialogs with Code::Blocks wxSmith •Updated translations --Added Spanish,Russian,German,Polish translation --Updated Chinese and Japanese translations •Other fixes and changes -
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CoreAmber is a Arm Processor structure 32 Bit comes from Amber processor the code is been written in CX & Verilog
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ALCHA
A New Programming Language for FPGA Projects
ALCHA aims to reduce FPGA project develop time by means of automation and abstraction, but without loosing the low-level control that HDLs, such as Verilog, provides. It will support an object oriented programming model, abstract data and signal types, and compile-time scripting. -
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UMHDL
Integrated Development Environment (IDE) for learning HDL
..., the interface developed acts as a front-end that allows writing code (with syntax highlighting), invokes an external VHDL compiler and simulator (such as GHDL), and displays the result of the simulation graphically as waveforms (invoking to GTKWave). -
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verilog_code_collection
my personal verilog code collection
some basic stuff, basic building blocks, which might result in some electric drive, DSP, microprocessor code... -
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flmodem
Fork of Fldigi allowing for much faster data over the FM 9600 port.
Flmodem is a sound card based modem that is used for higher-speed digital modes over an amateur radios 9600-port. It is a patch-set (small modification) applied on top of the normal Fldigi releases. The code modifications increase the usable audio bandwidth from 4000Hz up to 8000Hz. Program works as a pure-modem requiring external propgrams to operate (no tx/rx chat window) Can run simultaneously alongside Fldigi on the same computer. Currently there is only 1 modem which uses... -
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Program for creating Verilog synthesizable XOR trees for high performance designs. Supports creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers.
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Please, get the last version from http://sba.accesus.com/software-tools/sba-creator
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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CoolFormat
CoolFormat Source Code Formatter
CoolFormat Source Code Formatter is a code formatter for C\C++\C#\CSS\HTML\Java\JavaScript\JSON\Objective-C\PHP\SQL\Verilog\XML. It supports code highlighting for web publishment which is truly convenient for writing and reading a blog post, etc. CoolFormat source code formatting is a C\C++\C#\CSS\HTML\Java\JavaScript\JSON\PHP\SQL\XML code formatting tool. The software can quickly format in multiple styles and colorize the language. The interface adopts the style of Office 2010... -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
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DRAKON Editor
A free cross-platform editor for the DRAKON visual language.
DRAKON is a diagram language developed within the Russian space program. Its primary objective is presenting complex software systems in a way which is easy to understand by humans. DRAKON's motto: took a glance - understood at once. DRAKON Editor helps software architects, quality specialists and developers. Architects and quality assurers can express a high-level view of how their product works. DRAKON serves them to explain the dynamics of a software system. Software engineers can use... -
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Integrate green/free toolchains, For build same source code on Win/Linux conveniently. Language: [C] [C++] [ASM] [Verilog] [Python3] [Perl] With toolchains: [mingw32] for win [iverilog] (for win, Todo: Compile Script) [Python3.4] for win [NSAM 2.11.08] for win [Tinyperl]for win
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The QuAd library contains MATLAB codes for generating verilog codes of any configuration of QuAd. It also contains functional MATLAB model of QuAd that can be used for simulations at higher abstraction levels. The library also includes PMF and Error Estimation code for QuAd configurations. This open-source library is developed to facilitate comparisons, and to facilitate research and development in AC at higher abstraction levels. In case of usage, please refer to our publication: M...
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bel_fft
FFT co-processor in Verilog based on the KISS FFT
bel_fft is a FFT co-processor that can calculate FFTs with arbitrary radix. It is a hardware implementation of the free software Kiss FFT ("Keep it simple, Stupid!"). The target was to allow a simple replacement of the software code with the hardware implementation. Therefore bel_fft comes with a software driver that is compatible with the Kiss FFT routines. bel_fft also has a modular architecture and allows interfacing different bus architectures. So far AMBA AXI, Altera's Avalon bus... -
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ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
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ns2-wimax-awg
WIMAX Model for ns-2.36 implementing IEEE 802.16-2012 OFDMA.
The earlier version of this NS-2 add-on (for OFDM PHY) was developed at NIST. At the WiMAX Forum Plenary Meeting at Hawaii (January 30 - February 2, 2007), the decision to merge the independent development efforts supported by Application Architecture Task Group (AATG), WiMAX Forum and NIST was taken. In 2009 the source code was made available to public though the website http://community.4gdeveloper.com/ and is moved from Google code to sourceforge gain a broader attention. Credit is given...
