Program for creating Verilog synthesizable XOR trees for high performance designs. Supports creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers.

Features

  • ECC Generation/Checking
  • AES-GCM Multiplier Generator
  • GF2 Multiplier Generator

Project Samples

Project Activity

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License

BSD License

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Additional Project Details

Intended Audience

Telecommunications Industry

User Interface

Command-line, Java Swing

Programming Language

Java

Related Categories

Java Code Generators, Java Electronic Design Automation (EDA) Software

Registered

2008-11-15