Eclipse Verilog editor Discussion

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Topic	Posts	Views	Last Post
In/Out/Inout ports coloring in component/module and it's instantiation By D. Nitecki on Mon Aug 27, 2018 07:41 AM	2	764	By D. Nitecki on Thu Aug 30, 2018 11:00 AM
Any plans to support SystemVerilog By Andi on Fri Mar 09, 2018 02:18 PM	1	220	By Andi on Fri Mar 09, 2018 02:18 PM
Veditor misunderstand parameter bitwidth. By sounansu on Sun Sep 27, 2015 07:08 AM	1	417	By sounansu on Sun Sep 27, 2015 07:08 AM
Project documentation By aghoras on Mon Jun 08, 2015 03:06 PM	2	422	By sqrt123 on Wed Jul 29, 2015 09:09 PM
Donations? By nctnico on Mon May 25, 2015 12:34 PM	2	348	By aghoras on Mon Jun 08, 2015 03:02 PM
VHDL template uses non-standard packages By GenGumby on Tue Apr 21, 2015 02:02 AM	2	346	By aghoras on Tue Apr 21, 2015 02:23 PM
Hierarchy Tree Dump in a Makefile By pirotz on Thu Feb 19, 2015 03:26 PM	1	359	By pirotz on Thu Feb 19, 2015 03:26 PM
Can't submit Patch By HorstWe on Tue May 13, 2014 09:02 AM	5	385	By HorstWe on Thu May 15, 2014 05:45 AM
Combination of scientific notation and time units produces syntax error By paddl on Wed Oct 09, 2013 12:35 PM	2	336	By aghoras on Wed Oct 09, 2013 06:05 PM
AutoTasks in Verilog By Yangsu Kim on Tue Jul 02, 2013 01:49 PM	1	344	By Yangsu Kim on Tue Jul 02, 2013 01:49 PM
How to build a veditor project? By Andres on Tue Jun 18, 2013 02:38 PM	2	425	By aghoras on Tue Jun 18, 2013 07:04 PM
Ini-Editor recommendations? By Maximilian Girlich on Tue Mar 19, 2013 10:47 AM	1	137	By Maximilian Girlich on Tue Mar 19, 2013 10:47 AM
VHDL Lead By Micahel Snook on Mon Mar 22, 2010 12:36 PM	2	312	By aghoras on Mon Mar 29, 2010 05:30 PM
Do you know Sigasi a veditor clone ? ! By ILLICO on Mon Feb 01, 2010 09:14 AM	1	441	By ILLICO on Mon Feb 01, 2010 09:14 AM
Purpose By Protik on Mon Nov 16, 2009 04:55 AM	3	200	By Protik on Mon Nov 16, 2009 08:55 PM
>500k VHDL file - Outline does not work By Johann Swanepoel on Fri Nov 13, 2009 11:22 AM	3	202	By Sourcerer on Mon Nov 16, 2009 04:59 PM
How to By Protik on Mon Nov 16, 2009 04:52 AM	1	190	By Protik on Mon Nov 16, 2009 04:52 AM
building -> using jar By Simon Martineau on Fri May 08, 2009 03:35 PM	6	255	By Simon Martineau on Fri May 08, 2009 10:29 PM
Status of trunk By Chris Ostler on Sat Nov 17, 2007 09:03 PM	2	156	By aghoras on Tue Nov 20, 2007 10:38 PM
Hierarchy and Outline Don't Work By lain.ux on Sun Jun 17, 2007 01:46 PM	2	204	By lain.ux on Sat Sep 29, 2007 03:24 PM
Error Parser By KOBAYASHI Tadashi on Sat Dec 02, 2006 03:33 PM	9	670	By aghoras on Fri Jun 01, 2007 05:25 PM
I want to be part of this team. By Frank Tao on Thu Apr 19, 2007 10:10 AM	2	180	By aghoras on Thu Apr 19, 2007 03:14 PM
Build command By aghoras on Tue Dec 05, 2006 05:56 PM	2	224	By KOBAYASHI Tadashi on Sun Dec 17, 2006 03:57 PM
Adding a ModelSim button to veditor By Øyvind Harboe on Thu May 04, 2006 06:56 AM	6	1208	By aghoras on Thu Dec 14, 2006 06:06 PM
VHDL Parser By aghoras on Thu Dec 07, 2006 05:08 PM	1	263	By aghoras on Thu Dec 07, 2006 05:08 PM

1 2 > >> (Page 1 of 2)

Eclipse Verilog editor Discussion

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Open Discussion

In/Out/Inout ports coloring in component/module and it's instantiation

Any plans to support SystemVerilog

Veditor misunderstand parameter bitwidth.

Project documentation

Donations?

VHDL template uses non-standard packages

Hierarchy Tree Dump in a Makefile

Can't submit Patch

Combination of scientific notation and time units produces syntax error

AutoTasks in Verilog

How to build a veditor project?

Ini-Editor recommendations?

VHDL Lead

Do you know Sigasi a veditor clone ? !

Purpose

>500k VHDL file - Outline does not work

How to

building -> using jar

Status of trunk

Hierarchy and Outline Don't Work

Error Parser

I want to be part of this team.

Build command

Adding a ModelSim button to veditor

VHDL Parser

Eclipse Verilog editor Discussion

Forums

Help

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