D. Nitecki

I have found that the coloring behavior is different in Verilog and VHDL. In Verilog in/out/inout port coloring is propagating through the whole file, but in VHDL the port coloring is limited only to the entity. (for Verilog and VHDL) I think adding coloring also to component/module and it's instantiation would speed up making connections.

I have found that the coloring behavior is different in Verilog and VHDL. In Verilog in/out/inout port coloring is propagating through the whole file, but in VHDL the port coloring is limited only to the entity. (for Verilog and VHDL) I think adding coloring also to component/module and it's instantiation would speed up making connections.

I have found that the coloring behavior is different in Verilog and VHDL. In Verilog in/out/inout port coloring is propagating through the whole file, but in VHDL the port coloring is limited only to the entity. (for Verilog and VHDL) I think adding coloring also to component/module and it's instantiation would speed up making connections.

This plugin is great! I like ports coloring in entity and I think adding coloring also to component/module and it's instantiation would speed up making connections. Making connections inside one entity when having a lot of modules is a pain - you always need to check ports directions (e.g. to make open ports for outputs and zeros for inputs).